Method for programming a memory structure

1. A method for programming a memory structure, the memory structure comprising a plurality of memory cells where each memory cell has a substrate, a source located on the substrate, a drain located on the substrate, a charge storage device located between the source and the drain, and a gate located on the charge storage device and between the source and the drain, the plurality of memory cells comprising a first memory cell and a second memory cell located on an identical bit line (BL) adjacent to the first memory cell, the method comprising:

providing a first gate biasing voltage and a second gate biasing voltage to the gates of the first memory cell and the second memory cell, respectively;

boosting an absolute value of a channel voltage of the first memory cell to generate electron and hole pairs at the drain of the second memory cell through gate-induced drain leakage or band-to-band tunneling, wherein the first gate biasing voltage is greater than the channel voltage of the first memory cell, and the channel voltage of the first memory cell is greater than the second gate biasing voltage; and

injecting the electron of the generated electron and hole pairs into the charge storage device of the first memory cell to program the first memory cell;

wherein the substrate is a P-type substrate.

2. The method of claim 1 , wherein the plurality of memory cells further comprises a third memory cell located on the bit line, the first memory cell is located between the second memory cell and the third memory cell, and the step of boosting the absolute value of the channel voltage of the first memory cell comprises:

providing a third gate biasing voltage to the third memory cell for boosting an absolute value of a channel voltage of the third memory cell to increase the absolute value of the channel voltage of the first memory cell, wherein the first gate biasing voltage is greater than the third gate biasing voltage.

3. The method of claim 2 , wherein the first memory cell, the second memory cell, and the third memory cell are located at adjacent word lines (WL).

4. The method of claim 2 , wherein the plurality of memory cells further comprises a fourth memory cell located on the bit line, the second memory cell is located between the first memory cell and the fourth memory cell, and the method further comprises:

providing a fourth gate biasing voltage to the fourth memory cell for boosting an absolute value of a channel voltage of the fourth memory cell to turn off the second memory cell, wherein the first gate biasing voltage is greater than the fourth gate biasing voltage.

5. The method of claim 1 , wherein the bit line further comprises two transistors respectively located at a beginning terminal and an end terminal of the bit line, and the method further comprises:

turning off the two transistors.

6. The method of claim 1 , wherein the plurality of memory cells further comprises a fourth memory cell located on the bit line, the second memory cell is located between the first memory cell and the fourth memory cell, and the method further comprises:

providing a fourth gate biasing voltage to the fourth memory cell for boosting an absolute value of a channel voltage of the fourth memory cell to turn off the second memory cell, wherein the first gate biasing voltage is greater than the fourth gate biasing voltage.

7. The method of claim 6 , wherein the first memory cell, the second memory cell, and the fourth memory cell are located at adjacent word lines.

8. The method of claim 1 , wherein the charge storage device is a floating gate device or a charge trapping layer device.

9. The method of claim 1 , wherein each memory cell is capable of storing at least one bit.

10. The method of claim 1 , wherein the source and the drain of each memory cell are N-type, and an N-type concentration of the source and the drain closer to the substrate is greater than that closer to the charge storage device.

11. The method of claim 1 , wherein the memory structure is a non-volatile memory.

12. The method of claim 11 , wherein the memory structure comprises a NAND flash, a multiple-time programmable memory (MTP), or a one-time programmable memory (OTP).