Instructions for ordering execution in pipelined processes
View Patent ↗Ordering instructions for specifying the execution order of other instructions improve throughput in a pipelined multiprocessor. Memory write operations local to a CPU are allowed to occur in an arbitrary order, and constraints are placed on shared memory operations. Multiple sets of instructions are provided in which order of execution of the instructions is maintained through the use of CPU registers, write buffers in conjunction with assignment of sequence numbers to the instruction, or a hierarchical ordering system. The system ensures that an earlier designated instruction has reach a specified state of execution prior to a latter instruction reaching a specified state of execution. The ordering of operations allows memory operations local to a CPU to occur in conjunction with other memory operations that are not affected by such execution.
1. A computer system comprising:
multiple processors with a shared memory resource accessible by all processors, and non-shared memory local to a processor;
data elements organized and stored in said shared memory resource designed to support data manipulation functions; and
compiler directives to indicate an order of operation execution, the directives comprising:
a first instruction in communication with said processor to execute write operations in memory local to said processor in an arbitrary order;
a second instruction in communication with said processor and said shared memory resource to indicate a set of write operations to said shared memory resource to be conducted in a specified order; and
a special instruction in communication with said processor and said shared resource to force execution of said write operations to said shared memory resource to precede storage of a pointer from an existing element of said shared resource to a new element of said shared resource, wherein said pointer is stored in said shared resource.
2. The system of claim 1 , further comprising a first register to store a first instruction address and a second register to store a second instruction address.
3. The system of claim 2 , further comprising a third instruction to manage order of execution of said first and second instructions.
4. The system of claim 3 , wherein execution of said second instruction is responsive to said first instruction reaching a specified state of execution.
5. The system of claim 4 , wherein said specified state of execution is selected from the group consisting of: committing instruction execution, initiating memory access, completing a memory access, initiating an I/O access, completing an I/O access, and completing instruction execution.
6. The system of claim 1 , wherein said first and second instructions are assigned a sequence number to specify an order of instruction execution.
7. The system of claim 6 , wherein said sequence number is statically encoded within said instruction.
8. The system of claim 6 , wherein said sequence number is dynamically encoded within said instruction.
9. The system of claim 1 , further comprising a manager to place a range of instructions in a hierarchical order.
10. The system of claim 8 , further comprising a special instruction to maintain execution of said instruction in said hierarchical order.
11. A computer system, comprising:
multiple processors with a shared memory resource accessible by all processors, and non-shared memory local to a processor;
data elements organized in said shared memory resource designed to support data manipulation functions; and
compiler directives to indicate an order of operation execution, the directives comprising:
a first instruction in communication with said processor to allow write operations in non-shared memory local to said processor to occur in an arbitrary order;
a second instruction in communication with said processor and said shared memory resource to indicate a set of write operations to said shared memory resource to be conducted in a specified order, wherein write operations to said shared memory resource must execute prior to storage of a pointer from an existing element of said shared memory resource into a new element of said shared memory resource; and
a third instruction in communication with said processor and said shared memory resource to manage order of execution of said first and second instructions;
wherein execution of said second instruction is responsive to said first instruction reaching a specified state of execution and said specified state of execution is selected from the group consisting of: committing instruction execution, initiating memory access, completing a memory access, initiating an I/O access, completing an I/O access, and completing instruction execution.
12. The system of claim 11 , a first register to store a first instruction address and a second register to store a second instruction address.
13. The system of claim 11 , wherein said first and second instructions are assigned a sequence number to specify an order of instruction execution.
14. The system of claim 11 , further comprising a special instruction in communication with said processor and said shared resource to maintain execution of said instructions in said hierarchical order.