Reference buffer circuits for providing reference voltages
A reference buffer circuit provides a reference voltage at an output node and comprises a closed-loop branch comprising an amplifier and first and second MOS transistors and an open-loop branch comprising a third MOS transistor. A positive input terminal of the amplifier receives an input voltage. A gate of the first MOS transistor is coupled to the output terminal of the amplifier, and a source is coupled to a negative input terminal of the amplifier. A gate of the second MOS transistor is coupled to the drain of the first MOS transistor, a source is coupled to a first voltage source, and a drain is coupled to the source of the first MOS transistor. A gate of the third MOS transistor is coupled to the output terminal of the amplifier, and a source is coupled to the output node.
1. A reference buffer circuit for providing a reference voltage at an output node, comprising
a closed-loop branch comprising:
an amplifier having a positive input terminal for receiving an input voltage, a negative input terminal, and an output terminal;
a first metal oxide semiconductor transistor having a gate coupled to the output terminal of the amplifier, a source coupled to the negative input terminal of the amplifier, and a drain; and
a second MOS transistor having a gate coupled to the drain of the first MOS transistor, a source coupled to a first voltage source, and a drain coupled to the source of the first MOS transistor; and
an open-loop branch comprising:
a third MOS transistor having a gate coupled to the output terminal of the amplifier, a source coupled to the output node, and a drain.
2. The reference buffer circuit as claimed in claim 1 further comprising a fourth MOS transistor having a gate coupled to the drain of the third MOS transistor, a source coupled to the first voltage source, and a drain coupled to the output node.
3. The reference buffer circuit as claimed in claim 1 further comprising:
a first load unit coupled between the drain of the first MOS transistor and a second voltage source;
a second load unit coupled between the drain of the third MOS transistor and the second voltage source.
4. The reference buffer circuit as claimed in claim 3 , wherein the first, second, third, and fourth MOS transistor are NMOS transistors, the first voltage source is arranged to provide a signal ground, and the second voltage source is arranged to provide a supply voltage.
5. The reference buffer circuit as claimed in claim 3 , wherein the first, second, third, and fourth MOS transistor are PMOS transistors , the first voltage source is arranged to provide a supply voltage, and the second voltage source is arranged to provide a signal ground.
6. The reference buffer circuit as claimed in claim 1 , wherein a current amount flowing through the open-loop branch is N times a current amount flowing through the closed-loop branch.
7. A reference buffer circuit, comprising
a closed-loop branch comprising:
an amplifier for receiving an input voltage;
a source-follower transistor having a gate coupled to an output of the amplifier and a first terminal coupled to a negative input terminals of the amplifier; and
a first current transistor coupled to the first terminal of the source-follower transistor in series and having a gate coupled to a second terminal of the source-follower transistor; and
an open-loop branch comprising:
a driving transistor having a gate coupled to the output terminal of the amplifier and a first terminal for providing a reference voltage; and
a second current transistor coupled to the first terminal of the driving transistor in series and having a gate coupled to a second terminal of the driving transistor.
8. The reference buffer circuit as claimed in claim 7 , wherein a current amount flowing through the open-loop branch is N times a current amount flowing through the closed-loop branch.
9. The reference buffer circuit as claimed in claim 7 , wherein when the source-follower transistor and the driving transistor are PMOS transistors, the first and second current transistors act as current sources; when the source-follower transistor and the driving transistor are NMOS transistors, the first and second current transistors act as current sinks.
10. A reference buffer circuit for providing a first reference voltage at a first output node and a second reference voltage at a second output node, comprising:
a closed-loop branch comprising:
a first amplifier having a positive input terminal for receiving a first input voltage, a negative input terminal, and an output terminal;
a second amplifier having a positive input terminal for receiving a second input voltage, a negative input terminal, and an output terminal;
a first metal oxide semiconductor transistor having a gate coupled to the output terminal of the first amplifier, a source coupled to the negative input terminal of the amplifier, and a drain;
a second MOS transistor having a gate coupled to the output terminal of the second amplifier, a source coupled to the negative input terminal of the amplifier, and a drain coupled to the drain of the first MOS transistor; and
a third MOS transistor having a gate coupled to the drain of the second MOS transistor, a source coupled to a first voltage source, and a drain coupled to the source of the second MOS transistor; and
an open-loop branch comprising:
a fourth MOS transistor having a gate coupled to the output terminal of the first amplifier, a source coupled to the first output node, and a drain; and
a fifth MOS transistor having a gate coupled to the output terminal of the second amplifier, a source coupled to the second output node, and a drain coupled to the drain of the fourth MOS transistor.
11. The reference buffer circuit as claimed in claim 10 , wherein a current amount following through the open-loop branch is N times a current amount flowing through the closed-loop branch.
12. The reference buffer circuit as claimed in claim 10 further comprising a first current source coupled between the source of the first MOS transistor and a second voltage source.
13. The reference buffer circuit as claimed in claim 12 further comprising:
a sixth MOS transistor having a gate coupled to the drain of the fifth MOS transistor, a source coupled to the first voltage source, and a drain coupled to the second output node; and
a second current source coupled between the source of the fourth MOS transistor and the second voltage source.
14. The reference buffer circuit as claimed in claim 13 , wherein the first and fourth MOS transistors are NMOS transistors, the second, third, fifth, and sixth MOS transistor are PMOS transistors, the first voltage source is arranged provide a supply voltage, and the second voltage source is arranged to provide a signal ground.
15. The reference buffer circuit as claimed in claim 13 , wherein the first and fourth MOS transistors are PMOS transistors, the second, third, fifth, and sixth MOS transistor are NMOS transistors, the first voltage source is arranged to provide a signal ground, and the second voltage source is arranged to provide a supply voltage.
16. A reference buffer circuit:
a closed-loop branch comprising:
a first amplifier for receiving a first input voltage;
a second amplifier for receiving a second input voltage;
a first source-follower transistor having a gate coupled to an output terminal of the first amplifier and a first terminal coupled to a negative input terminal of the amplifier;
a second source-follower transistor having a gate coupled to the output terminal of the second amplifier, and a first terminal coupled to the negative input terminal of the second amplifier, and a second terminal coupled to a second terminal of the first source-follower transistor; and
a first current transistor coupled to the first terminal of the second source-follower transistor in series and having a gate coupled to the second terminal of the second source-follower transistor; and
an open-loop branch comprising:
a first driving transistor having a gate coupled to the output terminal of the first amplifier and a first terminal for providing a first reference voltage;
a second driving transistor having a gate coupled to the output terminal of the second amplifier, a first terminal for providing a second reference voltage, and a second terminal coupled to a second terminal of the first driving transistor; and
a second current transistor coupled to the first terminal of the second driving transistor in series and having a gate coupled to the second terminal of the second driving transistor.
17. The reference buffer circuit as claimed in claim 16 , wherein when the first source-follower transistor and the first driving transistor are PMOS transistors and the second source-follower transistor and the second driving transistor are NMOS transistors, the first and second current transistors act as current sinks; when the first source-follower transistor and the first driving transistor are NMOS transistors and the second source-follower transistor and the second driving transistor are PMOS transistors, the first and second current transistors act as current sources.
18. The reference buffer circuit as claimed in claim 16 , wherein a current amount flowing through the open-loop branch is N times a current amount flowing through the closed-loop branch.