Print engine controller for receiving dot data

1. A print engine controller for a pagewidth printhead, the controller comprising:

contone and bi-level decompression circuitry for decompressing a contone layer of compressed page data and a bi-level layer of compressed page data, respectively;

halftoner and compositor circuitry for halftoning the decompressed contone layer to associated bi-level versions and compositing the decompressed bi-level layer over the halftoned contone layers;

printhead interface circuitry for receiving the halftoned and composited data so as to generate print data suitable for printing by the printhead; and

line loader and formatter circuitry for receiving dot data from the halftoner and compositor circuitry to store the dot data for lines to be printed in memory circuitry of the controller and to format said lines into an order required by the printhead interface circuitry.

2. The print engine controller of claim 1 , further comprising tag encoder circuitry for establishing infrared tag data on infrared tags according to protocols associated with the compressed page data.

3. The print engine controller of claim 2 , wherein the halftoner and compositor circuitry composites the infrared tags with the halftoned and composited data.

4. The print engine controller of claim 1 , in which the contone decompression circuitry is in the form of JPEG decoder circuitry.

5. The print engine controller of claim 1 , in which the bi-level decompression circuitry is in the form of G4 fax decoder circuitry.

6. The print engine controller of claim 1 , further comprising buffer circuitry for buffering the transfer of data to the halftoner and compositor circuitry.

7. The print engine controller of claim 1 , in which the memory circuitry is in the form of DRAM.