Semiconductor memory device and refresh method for the same
View Patent ↗A refresh method for a semiconductor memory device features high noise resistance, lower power consumption, and lower cost. All word lines of one or more memory cell blocks that have not been selected in a self refresh mode are controlled to have a floating potential substantially at ground level. Even when a word line and a bit line are short-circuited, this control prevents destruction of memory cell information, which may be caused by noise, and also prevents generation of leakage current. A fuse, etc., for preventing generation of leakage current is unnecessary, so that lower cost is realized.
1. A method for refreshing at least one of a plurality of memory cell blocks of a semiconductor memory device in refresh mode, wherein the semiconductor memory device includes a plurality of word line drive circuits and a plurality of power supply control circuits, each of the plurality of word line drive circuits driving a word line of the corresponding memory cell block, each of the plurality of power supply control circuits supplying the corresponding word line drive circuit with a power supply for driving the word line, the method comprising:
selecting one of the plurality of memory cell blocks in the refresh mode;
activating one or more word line drive circuits associated with one or more memory cell blocks that have not been selected;
deactivating one or more power supply control circuits associated with one or more memory cell blocks that have not been selected, and
controlling one or more word lines, which are associated with the one or more memory cell blocks that have not been selected, to have a floating potential.
2. The method according to claim 1 , wherein the floating potential has a level substantially corresponding to ground.
3. The method according to claim 1 , wherein the floating potential is a negative potential.
4. The method according to one of claim 1 , wherein each of the plurality of power supply control circuits includes a first drive transistor for receiving a first power supply, and a second drive transistor, connected in series to the first drive transistor, for receiving a second power supply having a lower potential than the first power supply, with each drive transistor having a tailing current and the floating potential is determined by a tailing current ratio of the first and second drive transistors and by a threshold voltage of the first drive transistor.
5. The method according to claim 4 , wherein the tailing current ratio is set so that the tailing current of the first drive transistor is larger than the tailing current of the second drive transistor.