Liquid crystal display and panel therefor
View Patent ↗A thin film transistor array panel according to an embodiment of the present invention includes: a gate line; a data line intersecting the gate line; a thin film transistor connected to the gate line and the data line; a pixel electrode connected to the thin film transistor; and a shielding electrode electrically isolated from the data line, covering the data line at least in part, and having an aperture exposing the data line.
1. A thin film transistor array panel comprising:
an insulating substrate;
a gate line formed on the insulating substrate and having a gate electrode;
a gate insulating layer covering the gate line;
a semiconductor layer formed on the gate insulating layer over the gate electrode;
a data line intersecting the gate line and having a source electrode;
a drain electrode facing the source electrode with respect to the semiconductor layer;
a passivation layer covering the semiconductor layer, the data line and the drain electrode, and having a contact hole;
a pixel electrode formed on the passivation layer and connecting to the drain electrode through the contact hole; and
a shielding electrode disposed on the passivation layer and having a first part covering the gate line and a second part covering the data line,
wherein the second part of the shielding electrode has at least one aperture, the at least one aperture being disposed within the boundaries of the shielding electrode, and
wherein the shielding electrode is made of a transparent conductive material.
2. The thin film transistor array panel of claim 1 , wherein the aperture is formed over the data line and has a width narrower than the width of the data line.
3. The thin film transistor array panel of claim 1 , wherein the aperture is formed along a center line of the data line.
4. The thin film transistor array panel of claim 3 , wherein the shielding electrode covers edges of the data line.
5. The thin film transistor array panel of claim 1 , wherein the width of the first part is narrower than the width of the gate line.
6. The thin film transistor array panel of claim 1 , wherein the first part and the second part of the shielding electrode intersect over the place where the gate line and the data line intersect.
7. The thin film transistor array panel of claim 1 , wherein the pixel electrode has a first domain defining member formed in an upper region of the pixel electrode, and a second domain defining member formed in a lower region of the pixel electrode.
8. The thin film transistor array panel of claim 7 , wherein the first domain defining member extends in a first direction and the second domain defining member extends in a second direction.
9. The thin film transistor array panel of claim 8 , wherein an angle between the first direction and the second direction is about 90 degrees.
10. The thin film transistor array panel of claim 8 , wherein one of the first direction and the second direction has an angle of about 45 degrees with respect to the gate line and the data line.
11. The thin film transistor array panel of claim 1 , wherein the source electrode encompasses at least a part of the drain electrode.
12. The thin film transistor array panel of claim 1 , wherein the passivation layer comprises an organic insulator.
13. The thin film transistor array panel of claim 1 , further comprising a storage electrode overlapping the pixel electrode.
14. The thin film transistor array panel of claim 13 , wherein the shielding electrode and the storage electrode are supplied with substantially the same voltage.