IP Library Granted Patent US 7,781,315
Granted Patent B2
US 7,781,315 · App. 12/146,166 · Granted Aug 24, 2010

Finfet field effect transistor insulated from the substrate

Assignees: STMicroelectronics (Crolles 2) SAS; Interuniversitair Micro-Electronica Centrum
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Quick Facts
Patent No.
US 7,781,315
App. No.
12/146,166
Granted
Aug 24, 2010
Kind
B2
Abstract

A finFET field effect transistor is produced by the formation of an electrical junction between the thin fin portion of semiconductor material which forms the channel of the transistor and the circuit substrate. Doping particles are implanted in the substrate through a mask which is then subsequently used to form the thin fin portion of the channel. The channel of the finFET transistor is thus electrically insulated from the circuit substrate in the same manner as in MOS integrated circuits realized from bulk silicon substrates.

Claims (38)

1. A process for realizing a finFET field effect transistor on a substrate of an integrated electronic circuit, comprising the following steps:

forming a mask on a surface of the substrate, with said mask comprising an opening located above a part of an active portion of the substrate;

realizing an implantation of doping particles through the mask opening into said exposed part of the active portion of the substrate, so as to create in said exposed part of the active portion, an electrical doping of a first type; and

forming, by epitaxial growth from the part of the active portion which is exposed in the mask opening, a thin fin portion of crystalline semiconductor material comprising at least the channel of the transistor, the crystalline semiconductor material being doped with a second type of doping opposite the first type forming an insulating electrical junction with the first type doped part of the active portion of the substrate, the channel having an electrical direction of conduction parallel to the surface of the substrate and a height perpendicular to the surface of the substrate.

2. The process according to claim 1 , wherein the thin fin portion additionally comprises source and drain zones of the transistor.

3. The process according to claim 1 , wherein the thin fin portion is directly doped during the formation by epitaxial growth.

4. The process according to claim 1 , wherein the thin fin portion is doped subsequent to completion of the formation by epitaxial growth.

5. A method, comprising:

forming a mask on a surface of a substrate, said mask including an elongated opening exposing an active portion of the substrate and defining a trench;

implanting a first type of doping particles through the elongated opening into said exposed active portion so as to create a doped region in the substrate having edges defined by the elongated opening;

epitaxially growing a thin fin portion of crystalline semiconductor material to fill at least a portion of the trench and provide at least a channel of a transistor; and

doping the thin fin portion of the crystalline semiconductor material with a second type of doping particles opposite the first type to form an insulating electrical junction with the first type doped part of active portion of the substrate.

6. The method of claim 5 further comprising removing the mask to leave the thin fin portion above the surface of the substrate.

7. The method of claim 5 wherein opposed side edges of the thin fin portion are aligned with opposed edges of the doped region in the substrate in a direction perpendicular to the substrate surface.

8. The method of claim 5 further comprising forming a transistor gate portion in the form of a bridge structure which straddles over the thin fin portion.

9. The method of claim 8 wherein the gate portion extends in a direction perpendicular to a longer dimension of the thin fin portion.

10. The method of claim 8 wherein the gate portion includes opposite end regions extending down to contact the surface of the substrate on either side of the doped region in the substrate and a center region above the thin fin portion.

11. The method of claim 5 wherein doping the thin fin portion is performed concurrently with epitaxially growing the thin fin portion.

12. The method of claim 5 wherein doping the thin fin portion is performed subsequent to epitaxially growing the thin fin portion.

13. A process for realizing a finFET field effect transistor on a semiconductive substrate of an integrated electronic circuit, comprising the following steps:

forming a mask on a surface of the semiconductive substrate, with said mask comprising an opening located above a part of an active portion of the substrate;

implanting dopant of a first type through the mask opening into said exposed part of the active portion of the semiconductive substrate; and

epitaxially growing from the part of the active portion of the semiconductive substrate which is exposed in the mask opening, a thin fin portion of crystalline semiconductor material comprising at least the channel of the transistor, the crystalline semiconductor material being doped with a second type of dopant opposite the first type and forming an electrical junction at a contact interface between a top of the first type doped part of the active portion of the semiconductive substrate and a bottom of the channel of the second type doped epitaxially grown thin fin portion, the channel having an electrical direction of conduction parallel to the surface of the substrate and a height perpendicular to the surface of the substrate.

14. The process according to claim 13 , wherein the thin fin portion additionally comprises source and drain zones of the transistor.

15. The process according to claim 13 , wherein the thin fin portion is directly doped during the formation by epitaxial growth.

16. The process according to claim 13 , wherein the thin fin portion is doped subsequent to completion of the formation by epitaxial growth.

17. A method, comprising:

forming a mask on a surface of a monocrystalline substrate, said mask including an elongated opening exposing an active portion of the monocrystalline substrate and defining a trench;

implanting a first type of doping particles through the elongated opening into said exposed active portion so as to create a doped region in the monocrystalline substrate having edges defined by the elongated opening;

epitaxially growing a thin fin portion of crystalline semiconductor material to fill at least a portion of the trench and provide at least a channel of a transistor; and

doping the thin fin portion of the crystalline semiconductor material with a second type of doping particles opposite the first type to form an electrical junction of opposite dopants at a contact interface between a top of the first type doped part of active portion of the monocrystalline substrate and a bottom of the channel of the thin fin portion.

18. The method of claim 17 further comprising removing the mask to leave the thin fin portion above the surface of the substrate.

19. The method of claim 17 wherein opposed side edges of the thin fin portion are aligned with opposed edges of the doped region in the substrate in a direction perpendicular to the substrate surface.

20. The method of claim 17 further comprising forming a transistor gate portion in the form of a bridge structure which straddles over the thin fin portion.

21. The method of claim 20 wherein the gate portion extends in a direction perpendicular to a longer dimension of the thin fin portion.

22. The method of claim 20 wherein the gate portion includes opposite end regions extending down to contact the surface of the substrate on either side of the doped region in the substrate and a center region above the thin fin portion.

23. The method of claim 17 wherein doping the thin fin portion is performed concurrently with epitaxially growing the thin fin portion.

24. The method of claim 17 wherein doping the thin fin portion is performed subsequent to epitaxially growing the thin fin portion.

Assignments (3)
CHANGE OF NAME Recorded Feb 23, 2024
From: STMICROELECTRONICS SA
To: STMICROELECTRONICS FRANCE
Reel/Frame 066663/0136 →
CORRECTIVE ASSIGNMENT TO CORRECT THE SECOND ASSIGNEE PREVIOUSLY RECORDED ON REEL 021503 FRAME 0031. ASSIGNOR(S) HEREBY CONFIRMS THE THAT THE SECOND ASSIGNEE WAS NOT INCLUDED IN THE ORIGINALLY FILED COVERSHEET. Recorded Oct 10, 2008
From: LENOBLE, DAMIEN
To: STMICROELECTRONICS (CROLLES 2) SAS; INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM
Reel/Frame 021670/0405 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 9, 2008
From: LENOBLE, DAMIEN
To: STMICROELECTRONICS (CROLLES 2) SAS
Reel/Frame 021503/0031 →
Priority Claims (1)
FR 07 04568 · Jun 26, 2007 · national
Continuity (1)
Related Publication 20090001463A1 · Jan 1, 2009