THIN FILM TRANSISTOR ARRAY PANEL FOR LIQUID CRYSTAL DISPLAY
There are provided two subpixels opposite each other with respect to each data line. A pair of gate lines are provided for each row of pixels. A plurality of subsidiary signal lines are provided between the adjoining columns of the pixels. The data lines and the subsidiary signal lines are alternately arranged between the adjoining columns of the pixels. A storage wire is provided between the adjoining rows of the pixel 12+66s.
1 . A method of manufacturing a thin film transistor array panel for a liquid crystal display, the method comprising:
forming a gate wire over a substrate, the gate wire including first and second gate lines and first and second gate electrodes connected to the first and the second gate lines, respectively;
forming a gate insulating layer covering the gate wire;
forming a semiconductor layer over the gate insulating layer;
forming a data wire over the semiconductor layer, the data wire including first and second data lines, first and second source electrodes connected to the first and the second data line, first and second drain electrodes respectively separated from the first and second source electrodes and data connectors connecting the first and second data lines;
forming a passivation layer over the data wire, the passivation layer having an uneven surface and first and second contact holes exposing the first and the second drain electrodes respectively; and
forming first and second pixel electrodes respectively connected to the first and the second drain electrodes through the first and the second contact holes, wherein
a mask for forming at least one of the gate wire, the data wire, the semiconductor layer, the passivation layer and the pixel electrodes at a first area of the substrate is used to form the at least one of the gate wire, the data wire, the semiconductor layer, the passivation layer and the pixel electrodes at a second area of the substrate by rotating the mask 180 degrees.
2 . The method of claim 1 , wherein a mask for forming the passivation layer comprises a plurality of opaque portions and a plurality of transparent portions, the plurality of transparent portions including a first portion with a first width, and a second portion with a second width smaller than the first width, the first portion corresponding to the first and second contact holes, and the second portion corresponding to the data wire.
3 . The method of claim 1 , wherein the first and second gate lines and the first and second gate electrodes are formed simultaneously by depositing a conductive material over the substrate and patterning the conductive material.
4 . The method of claim 1 , wherein the first and second data lines, first and second source electrodes, first and second drain electrodes and data connectors are formed simultaneously by depositing a conductive material over the semiconductor layer and patterning the conductive material.
5 . The method of claim 1 , further comprising forming subsidiary wires over the semiconductor layer.
6 . A method of manufacturing a thin film transistor array panel for a liquid crystal display, the method comprising:
forming a gate wire over a substrate, the gate wire including first and second gate lines and first and second gate electrodes connected to the first and the second gate lines, respectively;
forming a gate insulating layer covering the gate wire;
forming a semiconductor layer over the gate insulating layer;
forming a data wire over the semiconductor layer, the data wire including first and second data lines, first and second source electrodes connected to the first and the second data line, first and second drain electrodes respectively separated from the first and second source electrodes and data connectors connecting the first and second data lines;
forming a passivation layer over the data wire, the passivation layer having an uneven surface and first and second contact holes exposing the first and the second drain electrodes respectively; and
forming first and second pixel electrodes respectively connected to the first and the second drain electrodes through the first and the second contact holes, wherein
a mask for forming the passivation layer comprises a plurality of opaque portions and a plurality of transparent portions, the plurality of transparent portions including a first portion with a first width, and a second portion with a second width smaller than the first width, the first portion corresponding to the first and second contact holes, and the second portion corresponding to the data wire.
7 . The method of claim 6 , wherein the first and second gate lines and the first and second gate electrodes are formed simultaneously by depositing a conductive material over the substrate and patterning the conductive material.
8 . The method of claim 6 , wherein the first and second data lines, first and second source electrodes, first and second drain electrodes and data connectors are formed simultaneously by depositing a conductive material over the semiconductor layer and patterning the conductive material.
9 . The method of claim 6 , further comprising forming subsidiary wires over the semiconductor layer.