Sample and hold circuit for a current mode pipelined analog-to-digital converter

1. A pipelined current mode analog-to-digital converter, comprising:

a plurality of stages each comprising:

a first sample and hold circuit configured to receive an analog signal having a current;

said sample and hold circuit having at least first and second outputs;

said first output comprising a current from a current copier configured to copy said analog signal;

said second output comprising a current from a current mirror configured to mirror said analog signal;

a current mode analog-to-digital converter configured to create a digital signal from said second output of said sample and hold circuit; and

a current mode digital-to-analog converter configured to convert said digital signal back to an analog signal, wherein an output of said digital-to-analog converter is subtracted from said first output of said sample and hold circuit.

2. The pipelined analog-to-digital converter of claim 1 , wherein said sample and hold circuit is a differential circuit.

3. The pipelined analog-to digital converter of claim 1 , wherein each of said plurality of stages further comprises a second sample and hold circuit connected in parallel with said first sample and hold circuit.

4. The pipelined analog-to digital converter of claim 3 , wherein said second sample and hold circuit comprises a first output connected to said digital-to-analog converter output, and a second output connected to said analog-to-digital converter input.

5. The pipelined analog-to digital converter of claim 1 , wherein said sample and hold circuit comprises a means for maintaining a voltage of said first output within a predetermined range of values.

6. The pipelined analog-to digital converter of claim 5 , wherein said means is a common mode amplifier.

7. The pipelined analog-to-digital converter of claim 6 , wherein said voltage at said first output is maintained substantially equal to a reference voltage of said common mode amplifier.

8. The pipelined analog-to-digital converter of claim 1 , wherein a first stage of said pipelined analog-to-digital converter comprises a voltage-to-current converter at a beginning of said first stage, configured to convert an analog signal having a voltage to an analog signal having a current.

9. The pipelined analog-to-digital converter of claim 8 , wherein said sample and hold circuit is also configured to act as said voltage-to-current converter.

10. The pipelined analog-to-digital converter of claim 1 , wherein said current from said current mirror is scaled differently from said analog input.

11. The pipelined analog-to-digital converter of claim 1 , wherein said sample and hold circuit comprises a means for adjusting current through first and second branches of said sample and hold circuit.

12. The pipelined analog-to-digital converter of claim 11 , wherein said means for adjusting current comprises a digital-to-analog converter.

13. The pipelined analog-to-digital converter of claim 12 , wherein said digital-to-analog converter comprises at least one additional transistor connected to at least one of said first and second branches.

14. The pipelined analog-to-digital converter of claim 13 , wherein said additional transistor is a diode connected transistor comprising a switch at a gate of said additional transistor.

15. The pipelined analog-to-digital converter of claim 1 , wherein said sample and hold circuit comprises at least one scaled output.

16. The pipelined analog-to-digital converter of claim 1 , wherein said sample and hold circuit comprises at least one resistor in series with a capacitor at a transistor gate in order to decrease a charge time of said transistor gate.

17. The pipelined analog-to-digital converter of claim 1 , wherein said first sample and hold circuit further comprises a third output, said third output being a current from a second current mirror configured to mirror said analog signal.

18. A pipelined current mode analog-to-digital converter stage, comprising:

first and second parallel sample and hold circuits configured to receive an analog signal having a current;

said first and second sample and hold circuits each comprising at least first and second outputs, said first output being a current from a current copier and said second output being a current from a current mirror; and

a current mode analog-to-digital converter configured to alternately output a digital signal of said second output of said first and second sample and hold circuits;

a current mode digital-to-analog converter to convert said digital signal to an analog signal,

wherein an output of said digital-to-analog converter is connected to said first output of each of said first and second sample and hold circuits.

19. The pipelined analog-to-digital converter stage of claim 18 , wherein said sample and hold circuit is a fully differential circuit.

20. A method for converting an analog signal to a digital signal, comprising:

sampling and holding an analog signal having a current using at least one current mode sample and hold circuit;

outputting a first output of said analog signal from a current copier of said at least one sample and hold circuit, and a second output of said analog signal from a current mirror of said at least one sample and hold circuit;

converting said second output to a digital signal using a current mode analog-to-digital converter;

converting said digital signal back to an analog signal using a current mode digital-to-analog converter; and

subtracting an output of said digital-to-analog converter from said first output.