IP Library Granted Patent US 8,242,380
Granted Patent B2
US 8,242,380 · App. 12/148,017 · Granted Aug 14, 2012

Printed circuit board substrate and method for constructing same

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Quick Facts
Patent No.
US 8,242,380
App. No.
12/148,017
Granted
Aug 14, 2012
Kind
B2
Abstract

A printed circuit board (PCB) substrate and method for construction of the same. In one embodiment, a first dielectric material is associated with a first current return layer and a second dielectric material is associated with a second current return layer. A first signal path layer is embedded in the first dielectric material and a second signal path layer is embedded in the second dielectric material, wherein the first and second signal path layers are substantially parallel to each other in a stack-up arrangement. An adhesive layer is interposed between the first dielectric material and the second dielectric material.

Claims (25)

1. A printed circuit board (PCB) substrate, comprising:

a first dielectric material associated with a first current return layer;

a first signal path layer embedded in said first dielectric material;

a second dielectric material associated with a second current return layer; a second signal path layer embedded in said second dielectric material, said second signal path layer being substantially parallel to said first signal path layer in a stack-up arrangement; and

an adhesive layer interposed between said first dielectric material and said second dielectric material, wherein said adhesive layer has a lower loss tangent than said first dielectric material;

wherein said adhesive layer comprises a material operable to substantially reduce attenuation due to an electrical coupling effect between a first signal trace disposed in said first signal path layer and a second signal trace disposed in said second signal path layer.

2. The PCB substrate as recited in claim 1 , wherein said adhesive layer has a higher glass transition point (T g ) than said first dielectric material.

3. The PCB substrate as recited in claim 1 , wherein said adhesive layer comprises a dielectric material selected from one of a two-sided adhesive tape, an adhesive film having a copper foil, an epoxy adhesive sheet, and an expanded polytetrafluoroethylene (ePTFE).

4. The PCB substrate as recited in claim 1 , wherein said first and second signal traces are electrically coupled in a differential mode.

5. The PCB substrate as recited in claim 1 , wherein said first and second signal traces are electrically coupled in a common mode.

6. The PCB substrate as recited in claim 1 , wherein said first dielectric material comprises a material selected from the group consisting of FR-4 material, pre-preg material, core material, and B-stage substrate material.

7. A method for constructing a printed circuit board (PCB) substrate, comprising:

providing a first dielectric material associated with a first current return layer;

providing a first signal path layer embedded in said first dielectric material;

providing a second dielectric material associated with a second current return layer;

providing a second signal path layer embedded in said second dielectric material, said second signal path layer being substantially parallel to said first signal layer in a stack-up arrangement;

providing an adhesive layer interposed between said first dielectric material and said second dielectric material; and

selecting said adhesive layer to include a material having a lower loss tangent than said first dielectric material;

selecting said adhesive layer to include a material operable to substantially reduce attenuation due to an electrical coupling effect between a first signal trace disposed in said first signal path layer and a second signal trace disposed in said second signal path layer.

8. The method as recited in claim 7 , further comprising selecting said adhesive layer to include a material having a higher glass transition point (T g ) than said first dielectric material.

9. The method as recited in claim 7 , further comprising curing said first dielectric material of said PCB substrate.

10. The method as recited in claim 7 , further comprising curing said second dielectric material of said PCB substrate.

11. The method as recited in claim 7 , further comprising curing said adhesive layer of said PCB substrate.

12. The method as recited in claim 7 , wherein said first and second signal traces are electrically coupled in a differential mode.

13. The method as recited in claim 7 , wherein said first and second signal traces are electrically coupled in a common mode.

Assignments (2)
TERMINATION AND RELEASE OF SECURITY IN PATENTS Recorded Jan 10, 2017
From: BANK OF AMERICA, N.A.
To: NORTEK, INC.; AIGIS MECHTRONICS, INC.; BROAN-MEXICO HOLDINGS, INC.; BROAN-NUTONE LLC; BROAN-NUTONE STORAGE SOLUTIONS LP; CES GROUP, INC.; CES INTERNATIONAL LTD.; CLEANPAK INTERNATIONAL, INC.; ELAN HOME SYSTEMS, L.L.C.; GATES THAT OPEN, LLC; GEFEN, LLC; GOVERNAIR CORPORATION; HC INSTALLATIONS, INC.; HUNTAIR, INC.; INTERNATIONAL ELECTRONICS, LLC; LINEAR LLC; LITE TOUCH, INC.; MAGENTA RESEARCH LTD.; MAMMOTH-WEBCO, INC.; NILES AUDIO CORPORATION; NORDYNE LLC; NORDYNE INTERNATIONAL, INC.; NORTEK INTERNATIONAL, INC.; NUTONE LLC; OMNIMOUNT SYSTEMS, INC.; OPERATOR SPECIALTY COMPANY, INC.; PACIFIC ZEPHYR RANGE HOOD, INC.; PANAMAX LLC; RANGAIRE GP, INC.; RANGAIRE LP, INC.; SECURE WIRELESS, INC.; SPEAKERCRAFT, LLC; TEMTROL, INC.; XANTECH LLC; ZEPHYR VENTILATION, LLC
Reel/Frame 041327/0089 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2015
From: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 037079/0001 →