Method of forming isolation structure for semiconductor integrated circuit substrate
View Patent ↗Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of the isolation structures are coplanar with the surface of the substrate. Field doping regions may be formed beneath the field oxide regions. To meet the demands of different devices, the isolation structures may have varying widths and depths.
1. A method of forming an isolation structure in a semiconductor substrate comprising:
depositing a first mask layer on the substrate;
depositing a second mask layer on the first mask layer;
patterning the second mask layer to form a first opening in the second mask layer;
etching the first mask layer through the first opening to form a second opening in the first mask layer;
implanting a first dopant of a first conductivity type through the second opening to form a first region of the first conductivity type under the second opening;
removing the second mask layer;
heating the substrate so as to form a first field oxide region in the second opening of the first mask layer;
forming a trench in the substrate;
depositing a first dielectric material in the trench;
removing a portion of the first dielectric material such that a surface of the first dielectric material is located at a first level below a second level of a surface of the substrate, thereby forming a first recess over a remaining portion of the first dielectric material;
removing a portion of the first field oxide region such that a surface of the first field oxide region is located at a third level below the second level, thereby forming a second recess over a remaining portion of the first field oxide region;
depositing a second dielectric material in the recesses; and
removing portions of the second dielectric material such that the entire surface of the second dielectric material in each of the first and second recesses is substantially coplanar with a surface of the substrate.
2. The method of claim 1 wherein the second dielectric material is relatively more resistant to removal by normal semiconductor etch processes as compared with the first dielectric material.
3. The method of claim 2 wherein the second dielectric material comprises one or more materials selected from the group consisting of silicon nitride and polyimide.
4. The method of claim 3 wherein the first dielectric comprises one or more materials from the group consisting of the doped and undoped silicon oxides and silicate glasses.
5. The method of claim 4 wherein the first dielectric material comprises borophosphosilicate glass.
6. The method of claim 1 wherein removing portions of the second dielectric material comprises chemical-mechanical polishing.
7. The method of claim 1 wherein removing portions of the second dielectric material comprises etching.