Multi-bit phase alignment for synchronization mark pattern matching

1. A method of detecting a synchronization mark, the method comprising:

reading a stream of bits from a storage medium, wherein the stream of bits is read as output from a matched filter upstream of a primary data detector;

performing pattern matching to determine whether a pattern of bits read from the storage medium, matches at least a portion of a synchronization mark;

recognizing in the stream of bits, a phase of a repeated pattern of N bits indicative of a synchronization field;

performing phase alignment to determine whether a location of the first bit of the pattern, is consistent with an expected location of the synchronization mark based upon the phase;

wherein the phase alignment is performed by comparing a number of the first bit with a modulo N counter reading;

wherein N=4;

wherein the phase alignment indicates the synchronization mark if, the phase is 0 and the reading of the modulo counter 4 is zero, the phase is 1 and the reading of the modulo 4 counter is zero, the phase is 1 and the reading of the modulo 4 counter is 1, the phase is 2 and the reading of modulo 4 counter is 2, or the phase is 3 and the reading of the modulo 4 counter is 3; and

indicating an existence of a synchronization mark only where the pattern matching and phase alignment are satisfied.

2. The method of claim 1 wherein the synchronization mark comprises a primary synchronization mark preceding a data region.

3. The method of claim 1 wherein the synchronization mark comprises a embedded synchronization mark located within a data region.

4. The method of claim 1 wherein the stream of bits is read as output from a primary data detector.

5. The method of claim 4 wherein the primary data detector comprises a Viterbi decoder.

6. The method of claim 1 wherein the stream of bits is read as output from the matched filter upstream of a Viterbi decoder.

7. An apparatus for detecting a synchronization mark, the apparatus comprising:

a first generator configured to generate a first signal indicating that a pattern of bits read from a storage medium matches at least a portion of a synchronization mark;

a second generator configured to generate a second signal indicating that a location of the first bit of the pattern, is consistent with an expected location of the synchronization mark based upon a phase of a repeated pattern of bits in a synchronization field; and

a comparator having a first node in electronic communication with the first generator and a second node in electronic communication with the second generator, the comparator configured to generate a third signal indicating an existence of a synchronization mark, only where the first signal and the second signal are received.

8. The apparatus of claim 7 wherein the comparator comprises an AND gate.

9. The apparatus of claim 7 wherein the second generator comprises a modulo N counter, wherein N=the number of phases in the repeated pattern.

10. The apparatus of claim 7 wherein N=4.

11. The apparatus of claim 10 wherein the second generator is configured to output the second signal if, the phase is 0 and the reading of the modulo 4 counter is zero, the phase is 1 and the reading of the modulo 4 counter is 1, the phase is 2 and the reading of the modulo 4 counter is 2, or the phase is 3 and the reading of the modulo 4 counter is 3.

12. The apparatus of claim 7 wherein the synchronization mark comprises a primary synchronization mark preceding a data region.

13. The apparatus of claim 7 wherein the synchronization mark comprises a embedded synchronization mark located within a data region.

14. An apparatus of claim 7 further comprising an equalizer with a matched filter configured to receive the bit stream and to generate a first equalized signal.

15. The apparatus of claim 14 , wherein the first equalized signal is generated from the lengthened equalization target comprising a mathematical convolution of a first and a second transfer function, the first transfer function comprising a predetermined equalization target for providing desired shaping to the read signal, and the second transfer function comprising a matched filter function providing a time-reversed component that is a time-reversed replica of a whitening filter component of the equalization target.

16. An apparatus for detecting a synchronization mark, the apparatus comprising:

a processor in electronic communication with a non-transistory computer readable storage medium, the non-transistory computer readable storage medium having stored thereon code configured to direct the processor to:

read a stream of bits from a storage medium;

perform pattern matching to determine whether a pattern of bits read from the storage medium, matches at least a portion of a synchronization mark;

recognize in the stream of bits, a phase of a repeated pattern of N bits indicative of a synchronization field;

perform phase alignment to determine whether a location of the first bit of the pattern, is consistent with an expected location of the synchronization mark based upon the phase;

indicate an existence of a synchronization mark, only where the pattern matching and phase alignment are satisfied; and

an AND gate configured to receive at a first input node, a first signal indicating a result of the pattern matching, and to receive at a second input node, a second signal indicating a result of the phase alignment.

17. The apparatus of claim 16 further comprising a modulo N counter configured to count the stream of bits.