Fast, efficient reference networks for providing low-impedance reference signals to signal processing systems
Reference network embodiments are provided for use in pipelined signal converter systems. The network embodiments are fast and power efficient and they generate low-impedance reference signals through the use of a complimentary common-drain output stage, at least one diode-coupled transistor inserted between transistors of the output stage, and a controller. The controller is configured to provide a backgate voltage to the diode-coupled transistor to thereby establish a substantially-constant output current. The controller is further configured to provide gate voltages to the output stage to establish top and bottom reference voltages about the diode-coupled transistor that are spaced from a common-mode voltage. This reference structure maintains a constant output current as the span between the top and bottom reference voltages is selectively altered. In different embodiments, the diode-coupled transistor is replaced with a bipolar junction transistor.
1. A reference network to provide reference voltages, comprising:
a complimentary common-drain output stage formed with top and bottom output transistors;
an output diode-coupled transistor having an output backgate and inserted between said top and bottom output transistors; and
a controller that is configured to establish top and bottom reference voltages about said output diode-coupled transistor and to provide a backgate voltage to said output backgate to establish a substantially-constant output current through said output diode-coupled transistor.
2. The network of claim 1 , wherein said controller is configured to have at least one control loop arranged to adjust the gates of said top and bottom output transistors to establish said top and bottom reference voltages.
3. The network of claim 2 , wherein said controller includes:
a first differential amplifier arranged to drive the gate of one of said top and bottom output transistors to establish said top and bottom reference voltages; and
a second differential amplifier arranged to drive the gate of the other of said top and bottom output transistors to space said top and bottom reference voltages about a common-mode voltage.
4. The network of claim 1 , wherein said controller includes:
first and second replica diode-coupled transistors respectively having first and second replica backgates coupled to said output backgate wherein one of said first and second replica diode-coupled transistors carries a bias current; and
a differential amplifier arranged to drive said first and second replica backgates to reduce a voltage difference between terminals of said first and second replica diode-coupled transistors.
5. The network of claim 4 , wherein:
one of said first and second replica diode-coupled transistors is coupled between first and second bias transistors that are respectively gate-coupled to said top and bottom output transistors; and
the other of said first and second replica diode-coupled transistors is coupled between a current source that provides said bias current and a third bias transistor that is gate-coupled to one of said top and bottom output transistors.
6. The network of claim 5 , wherein said controller is configured to have at least one control loop arranged to adjust the gates of said top and bottom output transistors to establish said top and bottom reference voltages.
7. The network of claim 6 , further including a voltage source that provides a voltage to said control loop.
8. The network of claim 7 , wherein said voltage source is a bandgap voltage source.
9. The network of claim 4 , wherein said output diode-coupled transistor is sized to have a first gate width and said first and second replica diode-coupled transistors are sized to have second gate widths less than said first gate width.
10. The network of claim 1 , wherein said output diode-coupled transistor is a pmos transistor.
11. The network of claim 1 , further including a resistor inserted between gate and drain of said output diode-coupled transistor to enhance network speed.
12. The network of claim 1 , further including a transistor inserted between gate and drain of said output diode-coupled transistor to receive a bias voltage and enhance network speed.
13. A reference network to provide reference voltages, comprising:
a complimentary common-drain output stage formed with top and bottom output transistors;
a bipolar junction inserted between said top and bottom output transistors; and
a controller that is configured to establish top and bottom reference voltages about said junction diode;
wherein said controller includes:
a first differential amplifier arranged to drive the gate of one of said top and bottom output transistors to establish said top and bottom reference voltages; and
a second differential amplifier arranged to drive the gate of the other of said top and bottom output transistors to space said top and bottom reference voltages about a common-mode voltage.
14. The network of claim 13 , wherein said junction is provided by a diode-coupled bipolar junction transistor.
15. A signal converter system that provides a digital code which corresponds to an analog input signal, comprising:
a pipelined arrangement of converter stages configured to provide said digital code in response to said analog input signal wherein at least one of said stages includes a multiplying digital-to-analog converter that responds to top and bottom reference voltages; and
a reference network that includes:
a complimentary common-drain output stage formed with top and bottom output transistors;
an output diode-coupled transistor having an output backgate and inserted between said top and bottom output transistors; and
a controller that is configured to establish said top and bottom reference voltages about said diode-coupled transistor and to provide an output backgate voltage to said output backgate to establish a substantially-constant output current through said output diode-coupled transistor.
16. The system of claim 15 , wherein said controller is configured to have at least one control loop arranged to adjust the gates of said top and bottom output transistors to establish said top and bottom reference voltages.
17. The system of claim 16 , wherein said controller includes:
a first differential amplifier arranged to drive the gate of one of said top and bottom output transistors to establish said top and bottom reference voltages; and
a second differential amplifier arranged to drive the gate of the other of said top and bottom output transistors to establish said common-mode voltage.
18. The system of claim 15 , wherein said controller includes:
first and second replica diode-coupled transistors respectively having first and second replica backgates coupled to said output backgate wherein one of said first and second replica diode-coupled transistors carries a bias current; and
a differential amplifier arranged to drive said first and second replica backgates to reduce a voltage difference between terminals of said first and second replica diode-coupled transistors.
19. The system of claim 18 , wherein:
one of said first and second replica diode-coupled transistors is coupled between first and second bias transistors that are respectively gate-coupled to said top and bottom output transistors; and
the other of said first and second replica diode-coupled transistors is coupled between a current source that provides said bias current and a third bias transistor that is gate-coupled to one of said top and bottom output transistors.