Burst-mode data recovery for multi-gigabit passive optical networks
View Patent ↗In a TDMA optical network, a clock data recovery module uses signal oversampling and preamble correlation together with enhanced performance modules to extract additional data from the upstream transmission signal. Information including duty cycle, ONT power estimation, signal noise and jitter can be extracted from the upstream signal using digital logic and used to tune network components and/or alleviate network conditions.
1. A data recovery system for a time division multiple access network, the data recovery system comprising:
a signal sampler that samples an input signal at a frequency higher than a frequency of the input signal to produce an oversampled signal;
a preamble correlator that detects a preamble in said oversampled signal;
a delimiter detector that detects a delimiter in said oversampled signal;
a finite state machine comprising:
a first state prior to detection of a preamble by said preamble correlator;
a second state after detection of said preamble and prior to detection of a delimiter by said delimiter detector; and
a third state after detection of said delimiter;
wherein the finite state machine controls extraction of data from the oversampled signal; and
a duty cycle measurement module controlled by said finite state machine that measures a duty cycle of said oversampled signal during said third state.
2. The data recovery system according to claim 1 further comprising a phase selector that determines a phase of said oversampled signal.
3. The data recovery system according to claim 2 wherein said phase selector compares said oversampled signal with segments of a preamble at multiple phases of an oversampling clock and selects a phase of said oversampling clock that has a correlation with said oversampled signal above a high threshold value or a correlation with said oversampled signal below a low threshold value.
4. The data recovery system according to claim 2 wherein said preamble correlator comprises a first correlator that compares said oversampled signal with at least one segment of a preamble at a first duty cycle and at least one further correlator that compares said oversampled signal with at least one segment of a preamble at a further duty cycle.
5. The data recovery system according to claim 4 wherein said preamble correlator determines a duty cycle of said oversampled signal during at least one of said first state and said second state.
6. The data recovery system according to claim 1 wherein said duty cycle measurement module comprises:
at least one comparator that compares at least one segment of said oversampled signal with a plurality of duty cycle bit widths; and
at least one counter for each duty cycle bit width that counts a match between said at least one segment and the respective duty cycle bit width.
7. The data recovery system according to claim 1 further comprising at least one power estimation module that determines a power level of a transmitter that transmitted said input signal, wherein said power estimation module comprises:
at least one bit buffer that stores at least a portion of said preamble; and
at least one counter that counts a number of digital one bits of said portion of said preamble.
8. The data recovery system according to claim 7 wherein said at least one bit buffer receives a signal at a start of said first state to store oversampled data in said bit buffer and receives a signal at a transition between said first state and said second state to hold the oversampled data in said bit buffer.
9. The data recovery system according to claim 1 further comprising at least one digital filter that filters said oversampled signal, wherein said at least one digital filter receives an N-bit segment of said oversampled signal, wherein said at least one digital filter comprises a plurality of flipped bit filters, wherein each flipped bit filter receives M consecutive input bits of said N-bit segment, and wherein the output of each flipped bit filter is determined by a flipped bit logic table.
10. The data recovery system according to claim 9 comprising N−M+1 flipped bit filters, wherein the value of M is equivalent to the ratio of the sampling frequency to the input signal frequency.
11. The data recovery system according to claim 9 wherein said output of each flipped bit filter comprises:
an interpretation value of the respective M input bits produced by said flipped bit logic table; and
an indication value whether one or more of the respective M input bits have a digital value different to a value of the interpretation value.
12. The data recovery system according to claim 11 further comprising at least one adder that adds the number of said indication values to calculate a number of flipped bits for the N-bit segment.
13. The data recovery system according to claim 1 further comprising at least one jitter estimation module that estimates jitter in said oversampled signal.