Liquid crystal display with low flicker and driving method thereof
View Patent ↗An exemplary liquid crystal display ( 20 ) includes gate lines ( 21 ), a gate driver ( 25 ) configured for receiving input signals, a comparator ( 28 ), a reference voltage generator ( 29 ) configured for outputting a reference voltage to the comparator, and a timing control circuit ( 27 ). The gate driver is further configured for driving the gate lines. Falling edges of waveforms of the input pulse signals drop gradually from a first voltage to a second voltage. The comparator is configured for receiving the input pulse signals and the reference voltage, and outputting a control signal according to the input pulse signals and the reference voltage. The timing control circuit is configured for receiving the control signal from the comparator, and, according to the control signal, outputting output enable signals to the gate driver to adjust gate signals applied to the gate lines.
1. A display, comprising:
a plurality of gate lines;
a gate driver configured for receiving input pulse signals, wherein falling edges of waveforms of the input pulse signals drop gradually from a first voltage to a second voltage, the gate driver further configured for driving the gate lines;
a reference voltage generator configured for outputting a reference voltage, the value of the reference voltage being between the values of the first and second voltages of the input pulse signals;
a comparator configured for receiving the input pulse signals and the reference voltage, and outputting a control signal according to the input pulse signals and the reference voltage; and
a timing control circuit configured for receiving the control signal from the comparator, and, according to the control signal, outputting output enable signals to the gate driver to adjust gate signals applied to the gate lines, wherein falling edges of waveforms of the gate signals drop gradually from the first voltage to the reference voltage;
wherein the reference voltage is adjustable, and the reference voltage is selectively set to be a constant value according to a desired line length of the falling edges of waveforms of the gate signals.
2. The display of claim 1 , wherein when the voltage values of the input pulse signals are greater than the reference voltage, the comparator is configured to output a high voltage control signal, such that the output enable signals outputted by the timing control circuit are low voltage signals, and the gate driver outputs gate signals normally.
3. The display of claim 1 , wherein when the voltage values of the input pulse signals are less than the reference voltage, the comparator is configured to output a low voltage signal, such that the output enable signals outputted by the timing control circuit are high voltage signals, and the gate driver outputs low voltage gate signals.