Semiconductor memory device with low standby current
View Patent ↗In an SRAM according to the present invention, an internal power supply voltage for a memory cell is applied to a back gate of each of P-channel MOS transistors included in an equalizer, a write driver, and a column select gate. Therefore, even if an internal power supply voltage for a peripheral circuit is shut off to reduce current consumption during standby, a threshold voltage of each of the P-channel MOS transistors is maintained at a high level, and hence a leakage current is small.
1. A semiconductor memory device driven by first and second power supply voltages during a normal operation, said second power voltage supplied to the semiconductor memory device being shut off during standby, the semiconductor memory device comprising:
a memory cell driven by said first power supply voltage and storing data,
a write/read circuit driven by said second power supply voltage and writing data into and reading data from said memory cell, and
a pair of bit lines connected to said memory cell,
said write/read circuit including a P-channel MOS transistor having a back gate receiving said first power supply voltage, having a source receiving said second power supply voltage, and having a drain connected to said memory cell, wherein
said write/read circuit includes
a decoder activating said memory cell during a write operation, and
a write circuit setting any one bit line in said pair of bit lines to said second power supply voltage and setting the other bit line to a ground voltage in accordance with a write data signal, and writing said write data signal into said memory cell activated by said decoder, and
said write circuit includes said P-channel MOS transistor provided to correspond to each of the bit lines and having the drain connected to said memory cell via the corresponding bit line.
2. A semiconductor memory device driven by first and second power supply voltages during a normal operation, said second power supply voltage supplied to the semiconductor memory device being shut off during standby, the semiconductor memory device comprising:
a memory cell driven by said first power supply voltage and storing data,
a write/read circuit driven by said second power supply voltage and writing data into and reading data from said memory cell, and
a pair of bit lines connected to said memory cell,
said write/read circuit including a P-channel MOS transistor having a back gate receiving said first power supply voltage, having a source receiving said second power supply voltage, and having a drain connected to said memory cell, wherein
said write/read circuit includes
a charging circuit charging said pair of bit lines to said second power supply voltage during a read operation,
a decoder activating said memory cell, and lowering a voltage of any one bit line in said pair of bit lines in accordance with data stored in said memory cell,
a gate circuit allowing a potential difference produced between said pair of bit lines in accordance with data stored in said memory cell activated by said decoder to be transmitted to a pair of input/output nodes, and
a sense amplifier amplifying said potential difference between said pair of input/output nodes, and
each of said charging circuit and said gate circuit has said P-channel MOS transistor provided to correspond to each of the bit lines and having the drain connected to said memory cell via the corresponding bit line.
3. The semiconductor memory device according to claim 1 , wherein said semiconductor memory device is of a static type.
4. A semiconductor memory device driven by first and second power supply voltages during a normal operation, said second power supply voltage supplied to the semiconductor memory device being shut off during standby, the semiconductor memory device comprising:
a memory cell driven by said first power supply voltage and storing data;
a write/read circuit driven by said second power supply voltage and writing data into and reading data from said memory cell,
said write/read circuit including a P-channel MOS transistor having a source receiving said second power supply voltage, and having a drain connected to said memory cell; and
a pull-up circuit providing said first power supply voltage to a gate of said P-channel MOS transistor during said standby to thereby bring said P-channel MOS transistor out of conduction.
5. The semiconductor memory device according to claim 4 , further comprising a pair of bit lines connected to said memory cell, wherein
said write/read circuit includes
a decoder activating said memory cell during a write operation, and
a write circuit setting any one bit line in said pair of bit lines to said second power supply voltage and setting the other bit line to a ground voltage in accordance with a write data signal, and writing said write data signal into said memory cell activated by said decoder, and
said write circuit includes said P-channel MOS transistor provided to correspond to each of the bit lines and having the drain connected to said memory cell via the corresponding bit line.
6. The semiconductor memory device according to claim 4 , further comprising a pair of bit lines connected to said memory cell, wherein
said write/read circuit includes
a charging circuit charging said pair of bit lines to said second power supply voltage during a read operation,
a decoder activating said memory cell, and lowering a voltage of any one bit line in said pair of bit lines in accordance with data stored in said memory cell,
a gate circuit allowing a potential difference produced between said pair of bit lines in accordance with data stored in said memory cell activated by said decoder to be transmitted to a pair of input/output nodes, and
a sense amplifier amplifying said potential difference between said pair of input/output nodes, and
each of said charging circuit and said gate circuit has said P-channel MOS transistor provided to correspond to each of the bit lines and having the drain connected to said memory cell via the corresponding bit line.
7. The semiconductor memory device according to claim 4 , wherein said semiconductor memory device is of a static type.
8. A semiconductor memory device driven by first and second power supply voltages during a normal operation, said second power supply voltage supplied to the semiconductor memory device being shut off during standby, the semiconductor memory device comprising:
a memory cell driven by said first power supply voltage and storing data; and
a write/read circuit driven by said second power supply voltage and writing data into and reading data from said memory cell,
said write/read circuit including
a first P-channel MOS transistor having a first threshold voltage, and
a second P-channel MOS transistor having a source receiving said second power supply voltage, having a drain connected to said memory cell, and having a second threshold voltage, an absolute value of said second threshold voltage being larger than an absolute value of said first threshold voltage.
9. The semiconductor memory device according to claim 8 , further comprising a pair of bit lines connected to said memory cell, wherein
said write/read circuit includes
a decoder activating said memory cell during a write operation, and
a write circuit setting any one bit line in said pair of bit lines to said second power supply voltage and setting the other bit line to a ground voltage in accordance with a write data signal, and writing said write data signal into said memory cell activated by said decoder, and
said write circuit includes said second P-channel MOS transistor provided to correspond to each of the bit lines and having the drain connected to said memory cell via the corresponding bit line.
10. The semiconductor memory device according to claim 8 , further comprising a pair of bit lines connected to said memory cell, wherein
said write/read circuit includes
a charging circuit charging said pair of bit lines to said second power supply voltage during a read operation,
a decoder activating said memory cell, and lowering a voltage of any one bit line in said pair of bit lines in accordance with data stored in said memory cell,
a gate circuit allowing a potential difference produced between said pair of bit lines in accordance with data stored in said memory cell activated by said decoder to be transmitted to a pair of input/output nodes, and
a sense amplifier amplifying said potential difference between said pair of input/output nodes, and
each of said charging circuit and said gate circuit has said second P-channel MOS transistor provided to correspond to each of the bit lines and having the drain connected to said memory cell via the corresponding bit line.
11. The semiconductor memory device according to claim 8 , wherein said semiconductor memory device is of a static type.