Programmable jitter generation circuit

1 . An integrated circuit comprising:

a serial transmitter;

a serial receiver; and

a serial connection providing communication between said serial transmitter and said serial receiver, wherein

said serial transmitter comprises:

a clock generator configured to generate a clock signal, said clock signal having a clock phase relative to a reference clock;

a serializer configured to receive and serialize, in dependence on said clock signal, data to be transmitted to said serial receiver;

a clock control unit coupled to said clock generator and configured to apply an alteration to said clock phase of said clock signal to stress test said serial receiver.

2 . An integrated circuit as claimed in claim 1 , wherein said alteration of said clock phase varies with a characteristic frequency determined by the clock control unit to degrade said communication.

3 . An integrated circuit as claimed in claim 1 , wherein said alteration of said clock phase varies in amplitude determined by the clock control unit to degrade said communication.

4 . An integrated circuit as claimed in claim 1 , wherein said clock control unit controls said clock generator by issuing a control signal.

5 . An integrated circuit as claimed in claim 4 , wherein said control signal is a digital control vector.

6 . An integrated circuit as claimed in claim 1 , wherein said clock generator comprises a phase interpolator to generate said clock signal.

7 . An integrated circuit as claimed in claim 6 , wherein said control signal is a digital control vector and said clock generator further comprises a digital to analog converter, said digital to analog converter converting said digital control vector into at least one analog control signal, said at least one analog control signal controlling operation of said phase interpolator.

8 . An integrated circuit as claimed in claim 1 , wherein said clock generator uses a variable delay line when generating said clock signal.

9 . An integrated circuit as claimed in claim 4 , wherein said control signal issued by said clock control unit is a representation of a modulation pattern, said modulation pattern being one of:

a square-wave modulation pattern;

a triangular-wave modulation pattern;

a saw-tooth modulation pattern;

a sinusoidal modulation pattern; and

a pseudo-random modulation pattern.

10 . An integrated circuit as claimed in claim 1 , wherein said clock control unit alters said clock phase of said clock signal by continuously incrementing said clock phase in a predetermined direction.

11 . A method of stress testing a serial receiver on an integrated circuit, comprising the steps of:

generating a clock signal in a serial transmitter on said integrated circuit, said clock signal having a clock phase relative to a reference clock;

receiving in said serial transmitter data to be communicated over a serial connection on said integrated circuit, said serial connection providing communication between said serial transmitter and said serial receiver;

serializing, in dependence on said clock signal, data to be transmitted to said serial receiver; and

altering said clock phase of said clock signal to stress test said serial receiver.

12 . An integrated circuit comprising:

a serial transmitter means for transmitting serial data, a serial receiver means for receiving serial data; and

a serial connection means for providing communication between said serial transmitter means and said serial receiver means, wherein

said serial transmitter means comprises:

a clock generator means for generating a clock signal, said clock signal having a clock phase relative to a reference clock;

a serializer means for receiving and serializing, in dependence on said clock signal, data to be transmitted to said serial receiver means;

a clock control means coupled to said clock generator means to apply an alteration to said clock phase of said clock signal to stress test said serial receiver means.