IP Library Granted Patent US 8,093,579
Granted Patent B2
US 8,093,579 · App. 12/154,552 · Granted Jan 10, 2012

Semiconductor chip having a reduced band offset in its p-doped region and method for producing the semiconductor chip

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Quick Facts
Patent No.
US 8,093,579
App. No.
12/154,552
Granted
Jan 10, 2012
Kind
B2
Abstract

A semiconductor chip ( 1 ) comprises a p-doped region (I) having a cladding layer ( 18 ) and a contact layer ( 21 ) between which a first interlayer ( 19 ) and a second interlayer ( 20 ) are arranged. A concentration of a first material component (B) within the first and the second interlayer ( 19, 20 ) changes in such a way that the band gap varies in a range lying between the band gap of the cladding layer ( 18 ) and the band gap of the contact layer ( 21 ). A method for producing a semiconductor chip of this type is also disclosed.

Claims (43)

1. A semiconductor chip comprising a p-doped region having a cladding layer and a contact layer, a first interlayer and a second interlayer being arranged between the cladding layer and the contact layer, and wherein a concentration y of a first material component within the first and the second interlayer changes such that a band gap within the first and the second interlayer varies in a range lying between a band gap of the cladding layer and the band gap of the contact layer, the cladding layer, the first interlayer, the second interlayer and the contact layer each containing a respective compound semiconductor material, a composition of the each respective compound being in accordance with the relationship:

C x B y(1-x) E (1-y)(1-x) A, where 0≦x≦1 and 0≦y≦1;

wherein B is a first material component, E is a second material component, C is a third material component and A is a fourth material component;

wherein the concentration y of the first material component within the first interlayer decreases in an order proceeding from the cladding layer towards the second interlayer and the concentration y of the first material component within the second interlayer decreases in an order proceeding from the first interlayer towards the contact layer; and

wherein the concentration y of the first material component starts in the second interlayer at a value that is higher than a final value of the concentration y in the first interlayer.

2. The semiconductor chip according to claim 1 , wherein a size of the band gap within the first interlayer decreases in an order proceeding from the cladding layer toward the second interlayer.

3. The semiconductor chip according to claim 1 , wherein the band gap within the second interlayer decreases in an order proceeding from the first interlayer toward the contact layer.

4. The semiconductor chip according to claim 1 , wherein the first material component is aluminum.

5. The semiconductor chip according to claim 1 , wherein the second material component is gallium.

6. The semiconductor chip according to claim 1 , wherein the fourth material component is phosphorus or arsenic.

7. The semiconductor chip according to claim 1 , wherein the cladding layer contains InAlP, the first interlayer contains InAlGaP, the second interlayer contains AlGaAs and the contact layer contains GaAs.

8. The semiconductor chip according to claim 1 , wherein the concentration y of the first material component within the first interlayer, on a side facing the cladding layer, is between 20% and 100% inclusive.

9. The semiconductor chip according to claim 8 , wherein the concentration y of the first material component within the first interlayer, on a side facing the cladding layer, is between 70% and 90% inclusive.

10. The semiconductor chip according to claim 1 , wherein the concentration y of the first material component within the first interlayer, on a side facing the second interlayer is between 0% and 50% inclusive.

11. The semiconductor chip according to claim 10 , wherein the concentration y of the first material component within the first interlayer, on a side facing the second interlayer is between 10% and 40% inclusive.

12. The semiconductor chip according to claim 1 , wherein the concentration y of the first material component within the second interlayer, on a side facing the first interlayer, is between 10% and 100% inclusive.

13. The semiconductor chip according to claim 12 , wherein the concentration y of the first material component within the second interlayer, on a side facing the first interlayer, is between 60% and 80% inclusive.

14. The semiconductor chip according to claim 1 , wherein the concentration y of the first material component within the second interlayer, on a side facing the contact layer, is between 0% and 50% inclusive.

15. The semiconductor chip according to claim 14 , wherein the concentration y of the first material component within the second interlayer, on a side facing the contact layer, is between 2% and 5% inclusive.

16. The semiconductor chip according to claim 1 , wherein a valence band extends continuously proceeding from the cladding layer towards the contact layer.

17. The semiconductor chip according to claim 1 , wherein the semiconductor chip has an active region arranged between the p-doped region and an n-doped region.

18. The semiconductor chip according to claim 1 , wherein the semiconductor chip is a laser diode chip.

19. A method for producing a semiconductor chip according to claim 1 , comprising the steps of:

growing the first interlayer onto the cladding layer;

growing the second interlayer onto the first interlayer; and

growing the contact layer onto the second interlayer.

20. The method according to claim 19 , wherein the second interlayer is grown onto the first interlayer without any interruption of growth.

21. The method according to claim 19 , wherein between growing the first and the second interlayer, a changeover is made from phosphorus-based growth to arsenic-based growth.

22. The method according to claim 21 , wherein the first and the second interlayer are grown at the same temperature.

23. The method according to claim 22 , wherein the temperature is approximately 700° C.

24. The method according to claim 22 , wherein an interruption of growth takes place after the second interlayer has been grown, the temperature being reduced within said interruption of growth.

25. The method according to claim 24 , wherein the temperature is reduced under arsine supporting pressure.

26. The method according to claim 24 , wherein the contact layer is grown at a temperature of approximately 550°.

27. The method according to claim 19 , wherein the first interlayer is doped with magnesium or zinc.

28. The method according to claim 19 , wherein the second interlayer is doped with carbon, magnesium or zinc.

29. The method according to claim 19 , wherein the concentration of the first material component is reduced continuously in the course of growing the first and the second interlayer.

30. A semiconductor chip comprising a p-doped region having a cladding layer and a contact layer, a first interlayer and a second interlayer being arranged between the cladding layer and the contact layer, and a concentration y of a first material component within the first and second interlayers changing such that a band gap within the first and second interlayers varies in a range lying between a band gap of the cladding layer and a band gap of the contact layer, the first material component being Al; wherein a concentration y of the first material component Al decreases proceeding in an order from the cladding layer towards the contact layer and changes discontinuously at a transition between the first and second interlayers.

31. A semiconductor chip comprising a p-doped region having a cladding layer and a contact layer, a first interlayer and a second interlayer being arranged between the cladding layer and the contact layer, and wherein a concentration y of a first material component within the first and the second interlayer changes such that a band gap within the first and the second interlayer varies in a range lying between a band gap of the cladding layer and the band gap of the contact layer, the cladding layer, the first interlayer, the second interlayer and the contact layer each containing a respective compound semiconductor material, a composition of the each respective compound being in accordance with the relationship:

C x B y(1-x) E (1-y)(1-x) A, where 0≦x≦1 and 0≦y≦1;

wherein B is a first material component, E is a second material component, C is a third material component and A is a fourth material component;

wherein the concentration y of the first material component within the first interlayer decreases in an order proceeding from the cladding layer towards the second interlayer and the concentration y of the first material component within the second interlayer decreases in an order proceeding from the first interlayer towards the contact layer;

wherein the concentration y of the first material component starts in the second interlayer at a value that is higher than a final value of the concentration y in the first interlayer; and

wherein the third material component is indium.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 3, 2020
From: OSRAM OPTO SEMICONDUCTORS GMBH
To: OSRAM OLED GMBH
Reel/Frame 051467/0906 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ADD THE NAME OF THE SECOND INVENTOR PREVIOUSLY RECORDED ON REEL 021545 FRAME 0173. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 16, 2008
From: MAYER, BERND; SCHMID, WOLFGANG
To: OSRAM OPTO SEMICONDUCTORS GMBH
Reel/Frame 021986/0512 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2008
From: MAYER, BERND
To: OSRAM OPTO SEMICONDUCTORS GMBH
Reel/Frame 021545/0173 →