System and method for managing addresses in a computing system

1. A method for retrieving and managing addresses of data amongst a bank of m buffers and a corresponding bank of m registers, wherein m is a positive integer, the method comprising:

receiving, at a first buffer of the m buffers, a request for an address;

obtaining the address from a corresponding first register of the m registers;

sending the address, received by said obtaining, to a destination;

storing the address, received by the obtaining, in the first buffer; and

clearing the contents of a second buffer of the m buffers, in response to any of said receiving, obtaining or storing, without clearing the contents of said first buffer.

2. The method of claim 1 , wherein said clearing comprises clearing the contents of the second buffer of the m buffers, in response to any of said receiving, obtaining or storing, without clearing the contents of any remaining buffers of the m buffers.

3. The method of claim 1 , wherein said second buffer is k buffers downstream from said first buffer, and k is a positive integer.

4. The method of claim 3 , wherein k<m.

5. The method of claim 3 , wherein m is an even number, and m=2k.

6. The method of claim 1 , wherein the registers are FIFO registers.

7. The method of claim 1 , further comprising, before said receiving, populating said registers with physical addresses.

8. A method for retrieving and managing physical addresses amongst a local node, a local memory, and a memory manager, the method comprising:

an initialization phase, comprising:

defining a program to be executed; and

establishing, in the local memory, a table of virtual addresses and corresponding fictitious physical addresses, the fictitious physical addresses corresponding to locations within the memory manager, each virtual address and corresponding fictitious physical address having a corresponding actual physical address of responsive data for execution of the program;

a first retrieval phase, comprising:

generating a virtual address at the local node;

retrieving, from the table, a fictitious physical address that corresponds to the generated virtual address;

entering the fictitious physical address and the corresponding virtual address into a buffer in the local node; and

utilizing, in conjunction with the memory manager, the retrieved fictitious address to obtain the actual physical address that corresponds to the virtual address;

a second retrieval phase, following the first retrieval phase, comprising:

generating, at the local node, a virtual address;

obtaining, from the buffer in the local node, a fictitious physical address corresponding to the virtual address; and

utilizing the retrieved fictitious address to obtain the actual physical address that corresponds to the virtual address;

wherein the first retrieval phase completes when the table is entered into the buffer in the local node; and

wherein, during the second retrieval phase, the local node will no longer need to access the table to complete the program regardless of the number of remaining instructions in the program.

9. The method of claim 8 , wherein the memory manager includes m buffers and m corresponding registers, wherein the local node has a c-level cache, where c is a positive integer greater than or equal to two, and the table includes (c+1)(m/2) virtual addresses and corresponding fictitious physical addresses.

10. The method of claim 8 , wherein said utilizing in the first and second retrieval phases comprises:

receiving, at the memory manager, the fictitious physical address;

identifying a first buffer of the m buffers that corresponds to the received fictitious physical address;

obtaining, using a corresponding first register of the m registers, the corresponding actual physical address;

sending the actual physical address, received by said obtaining, to the local node;

storing the actual physical address, received by the obtaining, in the first buffer; and

clearing the contents of a second buffer of the m buffers without clearing the contents of said first buffer.

11. The method of claim 10 , wherein said clearing comprises clearing the contents of the second buffer of the m buffers without clearing the contents of any remaining buffers of the m buffers.

12. The method of claim 10 , wherein the registers are FIFO registers.

13. The method of claim 10 , further comprising, during the initialization phase, populating said registers with the actual physical addresses.

14. The method of claim 8 , wherein said second buffer is k buffers downstream from said first buffer, and k is a positive integer.

15. The method of claim 14 , wherein k<m.

16. The method of claim 14 , wherein m is an even number, and m=2k.

17. A system for retrieving and managing addresses, comprising:

a memory portal processor comprising a bank of m buffers and a corresponding bank of m registers, where m is a positive integer, the memory portal processor configured to:

receive, at a first buffer of the m buffers, a request for an address, where m is a positive integer;

obtain the address from a corresponding first register of the m registers;

send the address, received by said obtaining, to a destination;

store the address, received by the obtaining, in the first buffer; and

clear the contents of a second buffer of the m buffers without clearing the contents of said first buffer.

18. The system of claim 17 , wherein said system is configured to clear the contents of the second buffer of the m buffers, in response to any of said receiving, obtaining or storing, without clearing the contents of any remaining buffers of the m buffers.

19. The system of claim 17 , wherein said second buffer is k buffers downstream from said first buffer, and k is a positive integer.

20. The system of claim 17 , wherein k<m.

21. The system of claim 17 , wherein m is an even number, and m=2k.

22. The system of claim 17 , wherein the registers are FIFO registers.

23. The system of claim 17 , wherein said system is configured to an initial step of populating said registers with physical addresses.

24. A system for retrieving and managing physical addresses, comprising:

a local node, a local memory, and a memory manager, configured to:

in an initialization phase:

define a program to be executed; and

establish, in the local memory, a table of virtual addresses and corresponding fictitious physical addresses, the fictitious physical addresses corresponding to locations within the memory manager, each virtual address and corresponding fictitious physical address having a corresponding actual physical address of responsive data for execution of the program;

in a first retrieval phase:

generate a virtual address at the local node;

retrieve, from the table, a fictitious physical address that corresponds to the generated virtual address;

enter the fictitious physical address and the corresponding virtual address into a buffer in the local node; and

utilize, in conjunction with the memory manager, the retrieved fictitious address to obtain the actual physical address that corresponds to the virtual address;

in a second retrieval phase, following the first retrieval phase:

generate, at the local node, a virtual address;

obtain, from the buffer in the local node, a fictitious physical address corresponding to the virtual address; and

utilize the retrieved fictitious address to obtain the actual physical address that corresponds to the virtual address;

wherein the first retrieval phase completes when the table is entered into the buffer in the local node; and

wherein, during the second retrieval phase, the local node will no longer need to access the table to complete the program regardless of the number of remaining instructions in the program.

25. The system of claim 24 , wherein the memory manager includes m buffers and m corresponding registers, wherein the local node has a c-level cache, where c is a positive integer greater than or equal to two, and wherein the table includes (c+1)(n/2) virtual addresses and corresponding fictitious physical addresses.

26. The system of claim 24 , wherein said utilization in the first and second retrieval phases comprises:

receiving, at the memory manager, the fictitious physical address;

identifying a first buffer of the m buffers that corresponds to the received fictitious physical address;

obtaining, using a corresponding first register of the m registers, the corresponding actual physical address;

sending the actual physical address, received by said obtaining, to the local node;

storing the actual physical address, received by the obtaining, in the first buffer; and

clearing the contents of a second buffer of the m buffers without clearing the contents of said first buffer.

27. The system of claim 26 , wherein said clearing comprises clearing the contents of the second buffer of the m buffers without clearing the contents of any remaining buffers of the m buffers.

28. The system of 26 , wherein said second buffer is k buffers downstream from said first buffer, and k is a positive integer.

29. The system of claim 28 , wherein k<m.

30. The system of claim 28 , wherein m is an even number, and m=2k.

31. The system of claim 26 , wherein the registers are FIFO registers.

32. The system of claim 26 , further comprising, during the initialization phase, populating said registers with the actual physical addresses.