Dual signaling format switch fabric with multiplex capability
View Patent ↗A serial channel switch circuit and modular packet switch using the serial channel switch circuits are disclosed. The serial channel switch circuit has a reconfigurable table for internal logical-to-physical channel switch translation. Depending on the slot in which a card containing such a serial channel switch circuit is inserted in the modular packet switch, its serial channel switch circuit may receive a different set of reconfigurable table values that are specific to that location. A global set of logical channel values can be applied to each card, which performs logical-to-physical channel mapping according to its location in the modular packet switch. Other embodiments are also described and claimed.
1. An integrated circuit comprising:
a plurality of serial channel serializers;
a plurality of serial channel deserializers;
a parallel crossbar switch;
a plurality of serial-to-parallel converters coupling the serial channel deserializers to inputs of the parallel crossbar switch;
a plurality of parallel-to-serial converters coupling outputs of the parallel crossbar switch to the serial channel serializers; and
a logical-to-physical channel mapper having a reconfigurable channel map, the logical-to-physical channel mapper accepting logical channel crossbar switch configuration input values and translating the configuration inputs, according to the reconfigurable channel map, to a physical input-to-output mapping that is applied to the parallel crossbar switch.
2. The integrated circuit of claim 1 , wherein a logical channel crossbar switch configuration input value can specify, according to the reconfigurable channel map, the physical input-to-output mapping for multiple parallel crossbar switch inputs and outputs.
3. The integrated circuit of claim 2 , wherein the reconfigurable channel map contains different logical channel crossbar switch configurations, corresponding to different peer integrated circuits that the integrated circuit is allowed to communicate with.
4. The integrated circuit of claim 2 , each valid logical channel crossbar switch configuration input value enabling the logical-to-physical channel mapper to retrieve a corresponding variable-length list of physical input-to-output mapping values from the reconfigurable channel map.
5. The integrated circuit of claim 4 , further comprising a sequencing circuit, a plurality of shadow registers, and a plurality of parallel crossbar switch programming registers, the sequencing circuit stepping through the variable-length list of physical input-to-output mapping values and using each value to program at least one shadow register, the plurality of parallel crossbar switch programming registers loading the contents of the shadow registers in parallel to configure the parallel crossbar switch.
6. The integrated circuit of claim 1 , each serial channel serializer having the capability to send backchannel messages, each serial channel deserializer having the capability to receive backchannel messages, the integrated circuit having circuitry to deliver a received backchannel message to any one of a plurality of the serial channel serializers.
7. The integrated circuit of claim 1 , each serial channel serializer having the capability to send backchannel messages, including a message portion and an error detect portion, each serial channel deserializer having the capability to receive backchannel messages and use the error detect portion of a backchannel message to determine whether the message portion of the backchannel message is valid.
8. The integrated circuit of claim 1 , each serial channel deserializer having the capability to receive, over a common serial channel, multiple multiplexed subchannels, each serial channel serializer having the ability to send, over a common serial channel, multiple multiplexed subchannels, the parallel crossbar switch capable of switching each subchannel separately and concurrently between its inputs and outputs.
9. The integrated circuit of claim 8 , each serial channel deserializer also having the capability to receive from a serial channel a single subchannel, and each serial channel serializer having the ability to send over a serial channel a single subchannel.
10. The integrated circuit of claim 8 , the integrated circuit capable of calculating cycling redundancy check (CRC) values for each subchannel and inserting the CRC values in their respective subchannel data streams prior to merging with other subchannel data streams, the integrated circuit capable of detecting the presence of CRC values on each received subchannel and performing CRC data integrity checks on each received subchannel.
11. The integrated circuit of claim 10 , the integrated circuit using a programmed data extent value to determine the length of data in a subchannel data stream over which a CRC value is calculated.
12. A modular packet switch comprising:
an electrical backplane having a plurality of line card slots and a plurality of switch fabric card slots, the backplane having serial channels connecting each line card slot to each switch fabric card slot;
a plurality of interchangeable line cards inserted in the line card slots; and
a plurality of interchangeable switch fabric cards inserted in the switch fabric card slots, each switch fabric card comprising at least one serial channel switch to communicate packet data across the backplane serial channels with the plurality of line cards, the serial channel switches switching packet data between the line cards,
each line card receiving and transmitting packets external to the switch, each line card comprising at least one serial channel switch to communicate packet data across the backplane serial channels with the plurality of switch fabric cards, at least one of the line card serial channel switches reorganizing a plurality of packet data streams passing between its line card and the backplane serial channels.
13. The modular packet switch of claim 12 , wherein reorganizing a plurality of packet data streams comprises changing the signaling format of the packet data streams.
14. The modular packet switch of claim 13 , wherein changing the signaling format comprises multiplexing multiple packet data streams into a common higher-data-rate packet data stream.
15. The modular packet switch of claim 12 , wherein reorganizing a plurality of packet data streams comprises applying a logical-to-physical channel mapping within at least one of the line card serial channel switches.
16. The modular packet switch of claim 15 , wherein the logical-to-physical channel mapping applied to one of the line card serial channel switches differs, among line cards, for the same logical channel input.
17. The modular packet switch of claim 15 , wherein the logical-to-physical channel mapping is dynamically reconfigurable.
18. The modular packet switch of claim 15 , wherein the logical-to-physical channel mapping applied to at least one of the line card serial channel switches depends on the current configuration of the switch fabric cards.
19. The modular packet switch of claim 15 , wherein the logical-to-physical channel mapping applied to at least one of the line card serial channel switches depends on the peer line card with which the line card serial channel switch is communicating.
20. The modular packet switch of claim 12 , at least two of the switch fabric card serial channel switches receiving a common logical channel configuration value and configuring a logical-to-physical channel mapping, in response to the common logical channel configuration value, that differ from each other.
21. The modular packet switch of claim 20 , wherein the logical-to-physical channel mapping on the switch fabric card serial channel switches is dynamically reconfigurable.
22. The modular packet switch of claim 12 , wherein the switch fabric card serial channel switches and line card serial channel switches are reconfigured according to a common logical channel configuration sent by a central scheduler to each serial channel switch.
23. The modular packet switch of claim 22 , wherein a single logical channel configuration instruction can be converted by each serial channel switch to configuration instructions for a plurality of physical channels.