Granted Patent B2

US 7,899,966 · App. 12/159,971 · Granted Mar 1, 2011

Abstract

Claims (40)

1. A method for distributing interrupt load to processors in a multiprocessor system, the method comprising:

executing a single current transaction with a first processor;

receiving an interrupt request during the execution of the single current transaction;

estimating a first transaction completion time for the single current transaction executed on the first processor;

estimating a second transaction completion time for a single current transaction executed on a second processor; and

re-directing the interrupt request to the second processor only when the second transaction completion time for the single current transaction executed on the second processor is less than the first transaction completion time for the single current transaction executed on the first processor.

2. A method as set forth in claim 1 , further comprising:

estimating a transaction completion time for each other processor in the multiprocessor system; and

re-directing the interrupt request to the processor having the least estimated transaction completion time.

3. A method as set forth in claim 2 , wherein the processors in the multiprocessor system are symmetric processors and the method further comprises: load balancing between the processors so that the processors operate at a virtually uniform load.

4. A method for distributing interrupt load to processors in a multiprocessor system, comprising:

executing a single current transaction with a first processor;

generating an interrupt request during the execution of the single current transaction and directing the interrupt request to the first processor; and

estimating a first transaction completion time for the single current transaction executed on the first processor at the time the interrupt request is generated;

estimating a second transaction completion time for a single current transaction executed on a second processor; and

re-directing the interrupt request to the second processor only when the second transaction completion time for the single current transaction executed on the second processor is less than the first transaction completion time for the single current transaction executed on the first processor.

5. A method as set forth in claim 4 , further comprising:

estimating a transaction completion time for each other processor in the multiprocessor system; and

re-directing the interrupt request to the processor having the least estimated transaction completion time.

6. A method as set forth in claim 5 , wherein the processors in the multiprocessor system are symmetric processors and the method further comprises: load balancing between the processors so that the processors operate at a virtually uniform load.

7. A method for distributing interrupt load to processors in a multiprocessor system, comprising:

executing current transactions with multiple processors where each single transaction is associated with one of the processors;

generating an interrupt request;

estimating a transaction completion time for the single transaction of each processor; and

directing the interrupt request to the processor having the least estimated transaction completion time.

8. A method as set forth in claim 7 , wherein the step of estimating a transaction completion time occurs periodically.

9. A method as set forth in claim 7 , wherein the step of estimating a transaction completion time for each processor occurs when the interrupt request is generated.

10. A method as set forth in claim 7 , further comprising the step of communicating the interrupt request to an intermediary processor prior to estimating the transaction completion time.

11. A method as set forth in claim 7 , wherein the processors are symmetric processors and the method further comprises: load balancing between the processors so that the processors operate at a virtually uniform load.

12. A system for distributing interrupt load, comprising:

multiple processors, each processor being capable of executing transactions;

an interrupt distributor in communication with the processors for distributing interrupt requests; and

the interrupt distributor is configured to estimate transaction completion times for a single transaction of each processor so that when each interrupt request is distributed, the interrupt request is assigned to the processor having the smallest transaction completion time of the single transaction.

13. A system as set forth in claim 12 , wherein the processors are synchronous and operate at a virtually constant frequency.

14. A system as set forth in claim 13 , wherein the processors define portions of a processor core.

15. A system as set forth in claim 13 , wherein the processors are discrete units and the system includes a main memory and a bus connecting the main memory to the processors.

16. A system as set forth in claim 15 further comprising:

cache memory associated in communication with each processor.

17. A system as set forth in claim 12 , wherein the processors are asynchronous and in addition to estimating the transaction completion times for each processor, the interrupt distributor tabulates the estimated transaction times for each processor at each available processor frequency.

18. A system as set forth in claim 12 , wherein the interrupt distributor is in communication with a transaction handler associated with each respective processor, each the transaction handler continually monitors the respective processor to estimate transaction completion times.

Assignments (17)