Nanowire tunneling transistor
A transistor comprises a nanowire ( 22, 22′ ) having a source ( 24 ) and a drain ( 29 ) separated by an intrinsic or lowly doped region ( 26, 28 ). A potential barrier is formed at the interface of the intrinsic or lowly doped region ( 26, 28 ) and one of the source ( 24 ) and the drain ( 29 ). A gate electrode ( 32 ) is provided in the vicinity of the potential barrier such that the height of the potential barrier can be modulated by applying an appropriate voltage to the gate electrode ( 32 ).
1. Transistor comprising a nanowire having a source and a drain separated by an intrinsic or lowly doped region, wherein a potential barrier is formed at the interface of the intrinsic or lowly doped region and one of the source and the drain, wherein a gate electrode is provided in the vicinity of the potential barrier such that the effective height and/or width of the potential barrier can be modulated by applying an appropriate voltage to the gate electrode.
2. Transistor according to claim 1 , wherein a barrier region is located inside the intrinsic or lowly doped region between the source and the drain.
3. Transistor according to claim 1 wherein the barrier is a highly doped semiconductor material.
4. Transistor according to claim 3 , wherein the semiconductor material forming the barrier region is indium arsenide while the adjacent intrinsic or lowly doped regions are made of silicon gallium arsenide.
5. Transistor according to claim 1 , wherein the barrier is made from a metal.
6. Transistor according to claim 1 , wherein the nanowire is grown on a semiconductor substrate.
7. Transistor according to claim 1 , wherein the nanowire has highly doped end portions forming the source and the drain of the transistor.
8. Transistor according to claim 5 , wherein the outer surface of the nanowire is covered by an insulating layer.
9. Transistor according to claim 8 wherein on the surface of the insulating layer a metal layer is deposited forming a gate electrode.
10. Transistor according to claim 8 , wherein the insulating layer is a dielectric layer or a wide band gap semiconductor forming a Schottky barrier to the gate electrode.
11. Transistor according to claim 10 , wherein the wide band gap semiconductor forming the Schottky barrier to the gate electrode contains a delta-doped layer.