Protected semiconductor device and method of manufacturing thereof
View Patent ↗The semiconductor device ( 100 ) comprises at least one semiconductor element ( 20 ), a metallization structure comprising a first ( 31 ) and a second line ( 32 ) and extending thereon a resistor. An electrically insulating protection layer ( 36 ) is present on the resistor ( 35 ) and is defined in a pattern that is substantially identical to the resistor pattern and has a temperature stability up to a temperature that is at least equal to a deposition temperature of a passivation layer ( 37 ) to be deposited thereon so as to cover the metallization structure. Both the resistor ( 35 ) and the protection layer ( 36 ) are deposited conformally on the metallization structure and any underlying substrate.
1. A semiconductor device comprising a semiconductor substrate with at least one semiconductor element, and a thin-film resistor and a metallization structure comprising a first and a second line, between which lines and on which lines the resistor extends according to a desired resistor pattern, and a passivation layer covering the metallization structure and the resistor, while leaving bond pads in the metallization structure exposed,
wherein an electrically insulating protection layer is present between the resistor and the passivation layer, which protection layer has a uniform thickness and is defined in a pattern that is substantially identical to the resistor pattern and has a temperature stability up to a temperature that is at least equal to a deposition temperature of the passivation layer.
2. A semiconductor device as claimed in claim 1 , wherein the resistor is part of a filter.
3. A semiconductor device as claimed in claim 1 , wherein the resistor has a resistive value of less than 100 Ω/□.
4. A semiconductor device as claimed in claim 1 , wherein the protection layer comprises an inorganic material and is deposited conformally.
5. A semiconductor device as claimed in claim 1 , wherein the semiconductor element is a protection element against electrostatic discharge and is coupled between a signal line between an input and an output and ground, while the resistor is defined in the signal line.
6. A semiconductor device as claimed in claim 5 , wherein the substrate comprises an electrically conductive substrate region, a first region of a first conductivity type, a second region of a second conductivity type adjoining a surface of the substrate and having an interface with the first region defining a junction, and wherein the substrate further comprises a third electrically conductive region extending within the first region from the junction to the substrate region.
7. A method of manufacturing a semiconductor device provided with a semiconductor substrate, comprising the steps of:
defining at least one semiconductor element in the semiconductor substrate;
covering the substrate with an insulating layer;
providing a metallization structure on the insulating layer and extending in holes through the insulating layer to a contact the at least one semiconductor element, which structure comprises a first and second line that are mutually insulated, and at least one bond pad;
applying a thin-film resistor layer on the metallization structure and the substrate;
applying an electrically insulating protection layer on the thin-film resistor, which protection layer has a temperature stability up to a temperature that is at least equal to a deposition temperature of a passivation layer;
patterning the resistor layer and the protection layer with the help of a photoresist material according to a desired resistor pattern, such that the resistor forms a connection between the first and the second line of the metallization structure, and
providing a passivation layer that leaves the at least one bond pad in the metallization structure exposed.
8. A method as claimed in claim 7 , wherein the patterning of the resistor layer and the protection layer is carried out with an isotropic dry etch.
9. A method as claimed in claim 7 , wherein the insulating layer is applied with a deposition technique at a temperature sufficiently low to prevent diffusion of charge carriers defined in regions in the substrate.
10. A method as claimed in claim 7 and a semiconductor device comprising a semiconductor substrate with at least one semiconductor element, and a thin-film resistor and a metallization structure court a first and a second line, between which lines and on which lines the resistor extends according to a desired resistor pattern, and a passivation layer covering the metallization structure and the resistor, while leaving bond pads in the metallization structure exposed,
wherein an electrically insulating protection layer is present between the resistor and the passivation layer, which protection layer has a uniform thickness and is defined in a pattern that is substantially identical to the resistor pattern and has a temperature stability up to a temperature that is at least equal to a deposition temperature of the passivation layer; and
wherein the protection layer has an interface with the passivation layer.
11. An intermediate product comprising a semiconductor substrate and a plurality of device structures, each of which structures comprises at least one semiconductor element, a thin-film resistor and a metallization structure comprising a first and a second line, between which lines and on which lines the resistor extends according to a desired resistor pattern, wherein an electrically insulating protection layer is present on top of the resistor, which protection layer is defined in a pattern that is substantially identical to the resistor pattern and has a temperature stability up to a temperature that is at least equal to a deposition temperature of a passivation layer deposited or to be deposited on top of the device structures.