IP Library Granted Patent US 7,964,451
Granted Patent B2
US 7,964,451 · App. 12/162,697 · Granted Jun 21, 2011

Solid state imaging device and method for fabricating the same

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Quick Facts
Patent No.
US 7,964,451
App. No.
12/162,697
Granted
Jun 21, 2011
Kind
B2
Abstract

A first oxide film ( 102 ) is formed on a semiconductor substrate ( 101 ). A first nitride film ( 103 ) is formed on first gate electrode formation regions of the first oxide film ( 102 ). A plurality of first gate electrodes ( 104 ) are provided on the first nitride film ( 103 ) so as to be spaced apart from one another with a predetermined distance therebetween. A second oxide film ( 105 ) covers upper part and side walls of each of the first gate electrodes ( 104 ). A sidewall spacer ( 106 ) of a third oxide film is buried in an overhang portion generated on each side wall of each of the first gate electrodes ( 104 ) covered by the second oxide film ( 105 ). A second nitride film ( 107 ) covers the second oxide film ( 105 ), the sidewall spacer ( 106 ) and part of the first oxide film ( 102 ) located between the first gate electrodes ( 104 ). A plurality of second gate electrodes ( 108 ) are formed on at least part of the second nitride film ( 107 ) located between adjacent two of the first gate electrodes ( 104 ).

Claims (16)

1. A method for fabricating a solid state imaging device, the method comprising:

a first step of forming a first oxide film and a first nitride film over a semiconductor substrate so that the first oxide film and the first nitride film are stacked in this order;

a second step of forming, on the first nitride film, a plurality of first gate electrodes so that the first gate electrodes are arranged so as to be spaced apart from one another with a predetermined distance therebetween;

a third step of forming a second oxide film so that the second oxide film covers upper part and side walls of each said first gate electrode;

a fourth step of forming a sidewall spacer of a third oxide film so that the sidewall spacer is buried in an overhang portion generated on each side wall of each said first gate electrode covered by the second oxide film;

a fifth step of forming a second nitride film so that the second nitride film covers the second oxide film, the sidewall spacer and part of the first nitride film located between the first gate electrodes;

a sixth step of forming a plurality of second gate electrodes on at least part of the second nitride film located between adjacent two of the first gate electrodes;

a seventh step of forming a fourth oxide film on the first nitride film after the first step and before the second step; and

an eighth step of forming a fifth oxide film on the second nitride film after the fifth step and before the sixth step, wherein:

in the second step, part of the first nitride film is remained between the first gate electrodes, and

a thickness of the second nitride film is adjusted so that a total of respective thicknesses of parts of the first nitride film and the second nitride film located under a bottom of each said second gate electrode is the same as a thickness of part of the first nitride film located under a bottom of each said first gate electrode.

2. The method of claim 1 , wherein a thickness of the second nitride film is 2 nm or more and 35 nm or less.

3. The method of claim 1 , wherein the first oxide film has a thickness of 10-50 nm.

4. The method of claim 1 , wherein the first nitride film located under the bottom of each said first gate electrode has a thickness of 20-100 nm.

5. The method of claim 2 , wherein the first oxide film has a thickness of 10-50 nm.

6. The method of claim 2 , wherein the first nitride film located under the bottom of each said first gate electrode has a thickness of 20-100 nm.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2015
From: PANASONIC CORPORATION
To: PANNOVA SEMIC, LLC
Reel/Frame 036065/0273 →
CHANGE OF NAME Recorded Mar 6, 2009
From: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
To: PANASONIC CORPORATION
Reel/Frame 022363/0306 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 25, 2008
From: NIISOE, NAOTO; HIRATA, KAZUHISA; YAMADA, TOHRU
To: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Reel/Frame 021587/0076 →