Processor Interrupt Selection
Processor selection procedures are described. In an implementation, one or more computer-readable media comprise instructions that are executable to cause a processor executing the instructions to select, based on a performance goal, which of a plurality of processors is to further handle a device interrupt and when the selected processor is available, notify the selected processor to further handle the device interrupt.
1 . A method comprising:
selecting, based on a performance goal, which of a plurality of processors is to further handle a device interrupt; and
when the selected processor is available, notifying the selected processor to further handle the device interrupt.
2 . The method of claim 1 , wherein the performance goal designates one or more of:
a particular said processor that initiated the input/output operation;
an idle said processor;
a hardware thread consuming data from the input/output operation;
a particular said processor that is scheduled to be running a processing thread for the input/output operation when an interrupt is scheduled to issue; or a particular said processor near the device when compared with other processors in the plurality of processors.
3 . The method of claim 1 , wherein a processor making the selection is one or more of:
on a motherboard with the selected processor;
included in a non-uniform memory access node with the selected processor;
in a common socket with the selected processor; or
makes use of a common bus with the selected processor.
4 . The method of claim 1 , further comprising when the selected processor is unavailable, iterating selecting, based on the performance goal, which of the plurality of processors is to further handle the device interrupt until an available processor is discovered from the plurality of processors.
5 . The method of claim 4 , wherein the selected processor is unavailable due to being in a low power state compared to when the selected processor is processing data.
6 . The method of claim 1 , wherein the plurality of processors are message signaled interrupt extended (MSI-X) compliant.
7 . The method of claim 1 , wherein to further handle the device interrupt is to process a second level interrupt.
8 . The method of claim 1 , further comprising maintaining a state of the selected processor for subsequent further handling for the device interrupt.
9 . A system comprising a plurality of processors communicatively coupled to a device to perform an input/output operation in which at least one said processor is configured to select, based on a performance goal, which of a plurality of processors is to further handle the device interrupt and notify the selected processor to further handle the device interrupt.
10 . The system of claim 9 , wherein the performance goal designates one or more of:
a particular said processor that initiated the input/output operation;
an idle said processor;
a hardware thread consuming data from the input/output operation;
a particular said processor that is scheduled to be running a processing thread for the input/output operation when an interrupt is scheduled to issue; or
a particular said processor near the device when compared with other processors in the plurality of processors.
11 . The system of claim 9 , wherein the processor is one or more of:
on a motherboard with the selected processor;
included in a non-uniform memory access node with the selected processor;
in a common socket with the selected processor; or
makes use of a common bus with the selected processor.
12 . The system of claim 9 , wherein further to further handle the device interrupt is to process a second level interrupt.
13 . The system of claim 9 , wherein the plurality of processors are message signaled interrupt extended (MSI-X) compliant.
14 . One or more computer-readable storage media comprising instructions that are executable to cause a processor executing the instructions to:
select, based on a performance goal, which of a plurality of processors is to further handle a device interrupt; and
when the selected processor is available, notify the selected processor to further handle the device interrupt.
15 . One or more computer-readable media as described in claim 14 , wherein the performance goal designates one or more of:
a particular said processor that initiated the input/output operation;
an idle said processor;
a hardware thread consuming data from the input/output operation;
a particular said processor that is scheduled to be running a processing thread for the input/output operation when an interrupt is scheduled to issue; or
a particular said processor near the device when compared with other processors in the plurality of processors.
16 . One or more computer-readable media as described in claim 14 , wherein the processor is one or more of:
on a motherboard with the selected processor;
included in a non-uniform memory access node with the selected processor;
in a common socket with the selected processor; or
makes use of a common bus with the selected processor.
17 . One or more computer-readable media as described in claim 14 , wherein to further handle the device interrupt is to process a second level interrupt.
18 . One or more computer-readable media as described in 14 , wherein the processor is message signaled interrupt extended (MSI-X) compliant.
19 . One or more computer-readable media as described in claim 14 , wherein the instructions are further configured to when the selected processor is unavailable, iterating selecting, based on the performance goal, which of the plurality of processors is to further handle the device interrupt until an available processor is discovered from the plurality of processors.
20 . One or more computer-readable media as described in claim 19 , wherein the selected processor is unavailable due to being in a low power state compared to when the selected processor is processing data.