Serial Peripheral Interface for a Transceiver Integrated Circuit
A protocol may be implemented in a smart transceiver device that contains the physical (PHY) and media access control (MAC) layers of a protocol stack. In various embodiments, a serial peripheral interface (SPI) based design may be used. A protocol is disclosed that may be used to provide control and data transfer to and from the smart transceiver device. In particular, an exemplary format for the protocol, the commands, and responses is disclosed. In a further embodiment, a method for mode synchronization that does not require the use of additional pins and can be accomplished with the standard SPI pins is disclosed. In another embodiment, a method that permits frame timing on the SPI bus to be restored without resetting the slave device is disclosed.
1 . A device in communication with a master control application via a full duplex Serial Peripheral Interface (SPI) link, comprising:
circuitry configured to place the device in a mode detect state after a reset of said device;
circuitry configured to receive at least one mode message from the master control application via the full duplex SPI link using a framed messaging protocol overlaid on the SPI link, wherein messages comprise a header and a variable length payload, the header comprises a command field and a length field, the length field representative of a size of said variable length payload; and
circuitry configured to enable the device to return an acknowledgment message to the master control application.
2 . The device of claim 1 , wherein four SPI modes are available, the modes defining an active clock edge and a phase of a data line of the SPI.
3 . The device of claim 1 , wherein said at least one mode message is detected one or more times.
4 . The device of claim 1 , wherein said at least one mode message is repeatedly transmitted until the wireless protocol transceiver returns an acknowledgement.
5 . The device of claim 1 , wherein said acknowledgment message is a byte message.
6 . The device of claim 1 , wherein the master control application is associated with a video game system.
7 . A method of maintaining synchronization between devices in communication via a Serial Peripheral Interface (SPI) Link, comprising:
receiving at least one message transmitted by a device via said SPI link and determining that the received message is invalid;
resetting the SPI link by repeatedly transmitting reset messages to said device until an acknowledgment message is received from said first device; and
entering a mode detect state, further comprising transmitting a mode command to said first device.
8 . The method of claim 7 , wherein said determining that the received message is invalid further comprises determining that an undefined command was received.
9 . The method of claim 7 , wherein said determining that the received message is invalid further comprises determining that a command was sent but no response was received.
10 . The method of claim 7 , wherein said determining that the received message is invalid further comprises determining that a frame length field was not valid.
11 . The method of claim 7 , wherein the reset command is a byte message.
12 . The method of claim 7 , wherein the acknowledgement message is a byte message, further comprising activating a Data Available interrupt line.
13 . The method of claim 7 , wherein a device that receives said acknowledgment message re-initializes an associated SPI port.
14 . The method of claim 7 , wherein said devices are associated with a video game system.
15 . A method of framing data in a Serial Peripheral Interface (SPI) full duplex link between devices in a gaming console or peripheral, comprising:
framing at least one header and a variable length payload, the header comprising a command field and a length field, the length field representative of a size of said variable length payload; and
appending messages within one frame when a device has more than one packet to transmit.
16 . The method of claim 15 , wherein an idle command byte is transmitted when no information is available for transfer.
17 . The method of claim 16 , wherein the idle command byte is 0x00.
18 . The method of claim 15 , wherein a master control application controls all transactions and transfers data whenever the master control application has a message to transmit.
19 . The method of claim 15 , wherein a slave device generates an interrupt to a master control application indicating that a message is ready to be read by the master control application.
20 . The method of claim 15 , wherein a chip select line must be in an active state prior to a frame transaction.