Electronic modules and methods for forming the same
View Patent ↗Electronic modules are formed by encapsulating microelectronic dies within cavities in a substrate.
1. A method for constructing an electronic module, the method comprising:
forming a fill hole in a first side of a substrate and a cavity in a second side of the substrate, the cavity in fluidic communication with the fill hole;
forming a post within the cavity by, at least in part, positioning a via chip within the cavity, the via chip comprising a matrix disposed around the post;
positioning a die within the cavity; and
injecting an encapsulant through the fill hole into the cavity to encapsulate the die positioned therein.
2. The method of claim 1 , wherein positioning the die within the cavity comprises:
disposing the die on a dielectric layer; and
disposing the dielectric layer over the second side of the substrate such that the die is disposed within the cavity.
3. The method of claim 1 , further comprising electrically connecting a second die to the encapsulated die.
4. The method of claim 3 , wherein at least a portion of the electrical connection comprises the post.
5. The method of claim 1 , further comprising forming at least one additional post during formation of the cavity.
6. The method of claim 5 , further comprising forming a conductive material over the at least one additional post and an interior surface of the cavity.
7. The method of claim 1 , wherein the matrix comprises silicon and the post comprises a metal.
8. The method of claim 1 , further comprising forming the via chip by defining a hole through a thickness of the matrix and forming a metal within the hole to form the post.
9. The method of claim 1 , further comprising forming at least one layer of conductive interconnects over the second side of the substrate.
10. The method of claim 1 , further comprising removing at least a portion of the first side of the substrate to expose at least a portion of the die.
11. The method of claim 10 , further comprising forming at least one layer of conductive interconnects over the exposed portion of the die.
12. The method of claim 10 , further comprising, prior to the removing, disposing a handle wafer over the second side of the substrate.
13. The method of claim 12 , further comprising forming a layer of temporary bonding material over the handle wafer prior to disposing the handle wafer over the second side of the substrate.
14. A structure comprising:
a substrate defining at least one fill hole in a first side thereof and a cavity in a second side thereof, the cavity in fluidic communication with the at least one fill hole;
a via chip positioned within the cavity, the via chip comprising a matrix disposed around a post formed within the cavity; and
a die at least partially encapsulated within the cavity by an encapsulant.
15. The structure of claim 14 , further comprising a dielectric layer disposed over the cavity and in contact with the die.
16. The structure of claim 14 , wherein a plurality of fill holes are in fluidic communication with the cavity.