Method and apparatus for an event tolerant storage circuit

1. An event tolerant circuit comprising:

an input coupled with a storage node that maintains a storage voltage level;

a feedback loop coupled with the storage node, the feedback loop configured to reinforce a first voltage level at the storage node; and

the feedback loop including a C-element having at least one input and at least one output, the feedback loop further including a delay element connected with the at least one input, the at least one output in communication with the storage node, the C-element configured to pass a first voltage level from the at least one input to the at least one output when the first voltage level at the at least one input to the C-element maintains the first voltage level for at least a delay time T, provided by the delay element, to reinforce the storage voltage level of the storage node, and to not pass the first voltage level from the at least one input to the at least one output when the first voltage level at the at least one input to the C-element does not maintain the first voltage level for at least the delay time T to prevent a glitch from altering the storage voltage level at the storage node,

wherein the delay element is configured to sample the storage voltage of the storage node.

2. The event tolerant circuit of claim 1 wherein the circuit comprises a d-latch.

3. The event tolerant circuit of claim 1 , wherein the delay element is directly coupled to an input of the at least one input of the C-element.

4. The event tolerant circuit of claim 3 wherein the delay element introduces the delay time T to provide the first voltage level at non-overlapping times to the C-element, the first voltage level being from the glitch.

5. The event tolerant circuit of claim 3 wherein the feedback loop further comprises:

a first inverter having an input and an output, the input of the first inverter being coupled to the storage node so as to invert the storage voltage level of the storage node; and

a second inverter coupled to the output of the C-element, the second inverter configured to invert the output voltage level of the first inverter;

wherein the delay element and the C-element are both connected with the output of the first inverter.

6. The event tolerant circuit of claim 1 further comprising a transmission gate positioned between the input and the storage node, the transmission gate configured to pass a voltage level to the storage node.

7. The event tolerant circuit of claim 6 further comprising a clock line coupled to the transmission gate, wherein the transmission gate passes the storage voltage when the clock line has a low value and substantially prevents the storage voltage level to pass through the transmission gate when the clock line has a high value.

8. The event tolerant circuit of claim 5 further comprising a clock line configured to regulate the second inverter in communication with the output of the C-element.

9. The event tolerant circuit of claim 1 further comprising a capacitor coupled to the storage node, wherein the capacitor is configured to receive and maintain the storage voltage level.

10. A method for preventing a glitch from altering a storage voltage level at a storage node comprising:

storing a first data value at a storage node, the first data value having a voltage level;

passing a second data value to the storage node, wherein the second data value is previously passed through a feedback loop including a logic gate having a first input and a first output and a delay element connected with the input of the logic gate; and

suppressing a glitch in the feedback loop, wherein suppressing the glitch in the feedback loop further comprises:

dividing a path of the glitch in the feedback loop into a first glitch path and a second glitch path;

passing the glitch through the delay element to delay the glitch on at least one of the glitch paths; and

passing the delayed glitch to the logic gate, wherein the logic gate receives a first glitch from the first glitch path and a second glitch from the second glitch path at different points in time, thereby causing the logic gate to eliminate the glitch from the feedback loop.

11. The method of claim 1 wherein the first data value and the second data value are substantially similar voltage levels.

12. The method of claim 10 wherein passing the delayed glitch includes, passing the first glitch to the first input of the logic gate and passing the second glitch to a second input of the logic gate at non-overlapping times.

13. The method of claim 10 wherein the duration of the glitch delay is based at least on a maximum duration of the glitch.

14. The method of claim 10 wherein the duration of the delay is greater than the maximum duration of the of the glitch.

15. The method of claim 10 further comprising comparing at least a first input data value at the first input of the logic gate to at least a second input data value at the second input of the logic gate, wherein the second input of the logic gate is the delayed glitch, and passing a previously held data value to the output of the logic gate when the first input data value is different then the second data input value.

16. The method of claim 15 further comprising passing an inverted data value to the output of the logic gate when the first input data value is substantially similar to the second input data value.

17. The method of claim 10 further comprising introducing a delay value into the circuit, the delay value determined by a gated C-element and the delay element, wherein the delay value does not affect a setup time and a hold time when the clock is low, further wherein the gated C-element excludes the delay value when the clock is low.

18. The method of claim 10 wherein suppressing the glitch in the feedback loop further comprises absorbing the glitch before the first time preceding the clock edge and absorbing the glitch after the second time following the clock edge.