SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

1 . A semiconductor device, comprising:

a first transistor of a first conductivity type having a first gate electrode formed above a first active region of a semiconductor substrate;

a first stress-inducing film formed over the first active region so as to cover the first gate electrode for applying a stress to a channel region of the first transistor;

a first insulating film formed on the first stress-inducing film and having a planar upper surface; and

a second insulating film formed on the first insulating film.

2 . The semiconductor device of claim 1 , wherein the first insulating film is absent above the first gate electrode.

3 . The semiconductor device of claim 1 , wherein the first insulating film is a film that applies no stress to the channel region of the first transistor.

4 . The semiconductor device of claim 1 , wherein the first insulating film is a film that applies, to the channel region of the first transistor, a stress of the same nature as that applied by the first stress-inducing film.

5 . The semiconductor device of claim 1 , wherein:

the first transistor is an n-type MISFET; and

the first stress-inducing film is a film that applies a tensile stress in a gate length direction to the channel region of the first transistor

6 . The semiconductor device of claim 1 , wherein:

the first transistor is a p-type MISFET; and

the first stress-inducing film is a film that applies a compressive stress in the gate length direction to the channel region of the first transistor.

7 . The semiconductor device of claim 1 , further comprising:

a second transistor of a second conductivity type having a second gate electrode formed above a second active region of the semiconductor substrate; and

a second stress-inducing film formed over the second active region so as to cover the second gate electrode for applying a stress of a different nature than that applied by the first stress-inducing film to a channel region of the second transistor,

wherein the second insulating film is formed on the second stress-inducing film and the first insulating film.

8 . The semiconductor device of claim 7 , wherein the second insulating film is a film that applies, to the channel region of the second transistor, a stress of the same nature as that applied by the second stress-inducing film.

9 . The semiconductor device of claim 7 , wherein:

the first transistor is an n-type MISFET;

the second transistor is a p-type MISFET;

the first stress-inducing film is a film that applies a tensile stress in a gate length direction to the channel region of the first transistor; and

the second stress-inducing film is a film that applies a compressive stress in the gate length direction to the channel region of the second transistor.

10 . The semiconductor device of claim 7 , wherein:

the first transistor is a p-type MISFET;

the second transistor is an n-type MISFET;

the first stress-inducing film is a film that applies a compressive stress in a gate length direction to the channel region of the first transistor; and

the second stress-inducing film is a film that applies a tensile stress in the gate length direction to the channel region of the second transistor.

11 . The semiconductor device of claim 7 , further comprising a first conductive pattern formed above a device isolation region between the first active region and the second active region, wherein:

a portion of the first conductive pattern that is formed on a side of the first active region is covered by the first stress-inducing film;

a portion of the first conductive pattern that is formed on a side of the second active region is covered by the second stress-inducing film; and

the first stress-inducing film and the second stress-inducing film are planarized above the first conductive pattern.

12 . The semiconductor device of claim 1 , further comprising a second conductive pattern formed above the first active region so as to oppose the first gate electrode, wherein:

the first stress-inducing film covers the second conductive pattern; and

the first insulating film fills in a gap between the first gate electrode and the second conductive pattern.

13 . The semiconductor device of claim 12 , wherein the second conductive pattern is a gate electrode of a third transistor formed above the first active region.

14 . A method for manufacturing a semiconductor device, the method comprising:

a step (a) of forming a first transistor having a first gate electrode above a first active region of a semiconductor substrate and forming a second transistor having a second gate electrode above a second active region;

a step (b) of forming a first stress-inducing film over the semiconductor substrate so as to cover the first gate electrode and the second gate electrode;

a step (c) of forming a first insulating film over the semiconductor substrate so as to cover the first stress-inducing film and then planarizing an upper surface of the formed first insulating film;

a step (d) of selectively removing a portion of the first insulating film and a portion of the first stress-inducing film that are formed above the second active region;

a step (e) of forming a second stress-inducing film over the semiconductor substrate so as to cover the second gate electrode and the first insulating film;

a step (f) of selectively removing a portion of the second stress-inducing film that is formed above the first active region; and

a step (g) of forming a second insulating film so as to cover the first insulating film and the second stress-inducing film.

15 . The method for manufacturing a semiconductor device of claim 14 , wherein the step (c) includes planarizing the first insulating film so that a portion of the first stress-inducing film that is formed above the first gate electrode is exposed through the first insulating film.

16 . The method for manufacturing a semiconductor device of claim 14 , wherein:

the step (a) includes forming a first conductive pattern above a device isolation region provided between the first active region and the second active region; and

the step (f) includes removing and planarizing a portion of the second stress-inducing film that is formed on the first stress-inducing film above the first conductive pattern by using a chemical mechanical polishing method.

17 . The method for manufacturing a semiconductor device of claim 14 , wherein:

the step (a) includes forming a second conductive pattern opposing the first gate electrode above the first active region; and

the step (c) includes forming the first insulating film so that the first insulating film fills in a gap between the first gate electrode and the first conductive pattern.

18 . The method for manufacturing a semiconductor device of claim 14 , wherein:

the first stress-inducing film is formed so as to apply a tensile stress in a gate length direction to a channel region formed under the first gate electrode; and

the second stress-inducing film is formed so as to apply a compressive stress in the gate length direction to a channel region formed under the second gate electrode.

19 . The method for manufacturing a semiconductor device of claim 14 , wherein:

the first stress-inducing film is formed so as to apply a compressive stress in a gate length direction to a channel region formed under the first gate electrode; and

the second stress-inducing film is formed so as to apply a tensile stress in the gate length direction to a channel region formed under the second gate electrode.

20 . The method for manufacturing a semiconductor device of claim 19 , wherein:

the first insulating film is formed so as to apply a stress of the same nature as that applied by the first stress-inducing film to a channel region formed under the first gate electrode; and

the second insulating film is formed so as to apply a stress of the same nature as that applied by the second stress-inducing film to a channel region formed under the second gate electrode.