Read channel apparatus for asynchronous sampling and synchronous equalization
View Patent ↗A read channel and method using that read channel are disclosed. The read channel comprises an analog to digital converter which asynchronously samples at a fixed rate an analog signal formed by reading a data track, where that data track was written to a data storage medium at a symbol rate and an interpolator interconnected with the analog to digital converter. The read channel further comprises a fractionally-spaced equalizer, where the interpolator provides an interpolated signal to the fractionally-spaced equalizer at an interpolation rate, where that interpolation rate is greater than the symbol rate. The fractionally-spaced equalizer forms a synchronous equalized signal. The read channel further comprises a gain control module interconnected with the fractionally-spaced equalizer, and a sequence detector interconnected with the gain control module.
1. A read channel, comprising:
an asynchronous analog to digital converter to asynchronously sample an analog signal formed by reading a data track at a rate greater than the first rate, wherein said data track was written to a data storage medium at a first rate;
an upsampler to oversample in the asynchronous domain said analog signal at a rate greater than said first rate, wherein said upsampler is interconnected with said asynchronous analog to digital converter;
an interpolator interconnected with said upsampler;
a fractionally-spaced equalizer interconnected with said interpolator, wherein said interpolator provides interpolated samples to said fractionally-spaced equalizer at an interpolation rate, and wherein said fractionally-spaced equalizer forms synchronous equalized samples at an equalization rate, wherein said interpolation rate is greater than or equal to said equalization rate, and wherein said interpolation rate is greater than said first rate;
a gain control module interconnected with said fractionally-spaced equalizer; and
a sequence detector interconnected with said gain control module;
a first feedback circuit comprising a timing control circuit interconnected with said sequence detector and with said interpolator;
a second feedback circuit comprising a least mean square update circuit interconnected with said sequence detector and said fractionally-spaced equalizer.
2. The read channel of claim 1 , further comprising a third feedback circuit interconnecting said sequence detector and said gain control module.
3. The read channel of claim 2 , wherein said second feedback circuit is decoupled from said third feedback circuit.
4. The read channel of claim 3 , wherein said sequence detector comprises a Partial Response Maximum Likelihood sequence detector.
5. The read channel of claim 3 , wherein said sequence detector comprises a Noise Predictive Maximum Likelihood sequence detector.
6. The read channel of claim 5 , wherein said Noise Predictive Maximum Likelihood sequence detector comprises a branch metric computation algorithm and a plurality of predictor filters, wherein said predictor filters are embedded into said branch metric computation algorithm, wherein each transition of said algorithm is associated with a different one of said plurality of predictor filters.