On-chip voltage supply scheme with automatic transition into low-power mode of MSP430

1. An integrated electronic device including circuitry for providing a single system supply voltage from a primary power supply, the circuitry comprising:

a high power (HP) stage coupled to the primary power supply and receiving the single system supply voltage and having an output node coupled to a supply system node for providing a HP system supply voltage level and a HP output current such that the HP stage is configured to be active in a full power mode; and

a low power (LP) stage coupled to the primary power supply for receiving the single system supply voltage and to the supply system node through a voltage follower for following a continuous fixed bias voltage and providing a LP supply voltage level and an LP output current such that the LP stage is configured to be active in a low power mode,

wherein the HP system supply voltage level is greater than the LP system supply voltage level and the voltage follower of the LP stage is back-biased to switch off in response to a voltage level at the supply system node becoming greater than the HP system supply voltage level and to be forward-biased and switch on in response to the voltage level at the supply system node becoming lower than the HP system supply voltage level, wherein the HP stage comprises a PMOS transistor having a source coupled to the primary power source and a drain coupled to the supply system node, wherein the circuit provides a smooth spike free transition from the high power mode to the low power mode.

2. The integrated electronic device according to claim 1 , wherein the voltage follower is a NMOS transistor having a drain coupled to the primary power supply and a source coupled to the supply system node.

3. The integrated electronic device according to claim 1 , wherein the HP stage comprises an amplifier for amplifying a reference voltage to serve as a gate voltage for the PMOS transistor.

4. An integrated electronic device including circuitry for providing a single system supply voltage from a primary power supply, the circuitry comprising:

a high power (HP) stage coupled to the primary power supply and receiving the single system supply voltage and having an output node coupled to a supply system node for following a continuous fixed bias voltage and providing a HP system supply voltage level and a HP output current such that the HP stage is configured to be active in a full power mode; and

a low power (LP) stage coupled to the primary power supply for receiving the single system supply voltage and to the supply system node through a voltage follower for providing a LP supply voltage level and an LP output current such that the LP stage is configured to be active in a low power mode,

wherein the HP system supply voltage level is greater than the LP system supply voltage level and the voltage follower of the LP stage is back-biased to switch off in response to a voltage level at the supply system node becoming greater than the HP system supply voltage level and to be forward-biased and switch on in response to the voltage level at the supply system node becoming lower than the HP system supply voltage level, wherein the HP stage and the LP stage are dimensioned such that the maximum HP output current is greater than the maximum LP output current, wherein the circuit provides a smooth spike free transition from the high power mode to the low power mode; and

further comprising a power on reset stage coupled to the supply system node.

5. The integrated electronic device according to claim 1 , further comprising a power on reset stage coupled to the supply system node.

6. The integrated electronic device according to claim 1 , wherein the HP stage is adapted to receive an enable signal to be switched off in going to a mode.

7. The integrated electronic device according to claim 2 , wherein the HP stage and the LP stage are dimensioned such that the maximum HP output current is greater than the maximum LP output current.

8. The integrated electronic device according to claim 1 , wherein the HP stage and the LP stage are dimensioned such that the maximum HP output current is greater than the maximum LP output current.

9. The integrated electronic device according to claim 3 , wherein the HP stage and the LP stage are dimensioned such that the maximum HP output current is greater than the maximum LP output current.

10. The integrated electronic device according to claim 2 , further comprising a power on reset stage coupled to the supply system node.

11. The integrated electronic device according to claim 1 , further comprising a power on reset stage coupled to the supply system node.

12. The integrated electronic device according to claim 3 , further comprising a power on reset stage coupled to the supply system node.

13. The integrated electronic device according to claim 4 , further comprising a power on reset stage coupled to the supply system node.

14. The integrated electronic device according to claim 2 , wherein the HP stage is adapted to receive an enable signal to be switched off in a power down mode.

15. The integrated electronic device according to claim 1 , wherein the HP stage is adapted to receive an enable signal to be switched off in a power down mode.

16. The integrated electronic device according to claim 3 , wherein the HP stage is adapted to receive an enable signal to be switched off in a power down mode.