FILTER CIRCUIT AND FILTERING METHOD FOR REMOVING CONSECUTIVE NOISE FROM SAMPLED DIGITAL SIGNALS

1 . A filter circuit for filtering an input signal in synchronism with a clock signal to output a first output signal, comprising:

a first delay circuit operative in synchronism with the clock signal to produce at least three signals which are delayed in relation to the input signal by respective periods corresponding to one clock, two clocks and three clocks respectively;

an average circuit averaging every two of the three delayed signals to calculate three average values;

a differential circuit operative to the first output signal for calculating a difference of each of the three average values calculated by said average circuit from the first output signal to produce three differential values;

a minimum value determination circuit determining which of the three differential values calculated by said differential circuit is a minimum differential value to output a second output signal which indicates the average value corresponding to the minimum differential value;

a selector selecting one of the three average values which corresponds to the second output signal to output the selected average value as a third output signal; and

a second delay circuit outputting the third output signal as the first output signal in synchronism with the clock signal,

whereby every two of the three delayed signals are averaged, and one of the average values is determined which is closest to the previous value of the first output signal, the averaged value determined being output as the current value of the first output signal.

2 . The filter circuit as claimed in claim 1 , wherein said average circuit includes three adders, wherein

one of said three adders averages two values of the input signal that are delayed by the periods corresponding to the one clock and the two clocks, respectively, to produce a first average value, and averages the first average value and the first output signal to thereby output one of the three average values,

another of said three adders averaging two values of the input signal delayed by the periods corresponding to the one clock and the three clocks, respectively, to thereby output another of the three average values,

still another of said three adders averaging two values of the input signal delayed by the periods corresponding to the two clocks and the three clocks, respectively, to thereby output still another of the three average values.

3 . The filter circuit as claimed in claim 1 , wherein said differential circuit calculates an absolute value of the difference of each of the three average values from the value of the first output signal.

4 . A filter circuit for removing noise from digital input data in a form of series of sampled values to produce digital output data in the form of series of filtered values, comprising:

a delay unit successively receiving the sampled values to output a current, previous and twice previous values at each time in synchronism with a sampling clock;

an average circuit receiving the current, previous and twice previous values to calculate an average value of every two of the current, previous and twice previous values to output the three average values calculated;

a determination circuit determining one of the three average values that is closest to the previous filtered value of the digital output data at each time in synchronism with a sampling clock; and

an output circuit calculating the filtered value of the digital output data by performing an averaging operation of the sampled values of which the closest average value is calculated.

5 . The filter circuit as claimed in claim 4 , wherein said average circuit performs the averaging operation together with the previous filtered value.