Method for using a multi-bit cell flash device in a system not designed for the device
View Patent ↗A computerized system is booted from a flash memory device configured to always operate one or more of its blocks only in a M-bit-per-cell mode and the rest of its blocks in a N>M-bit-per-cell mode. When the system is powered up, an initialization program is retrieved from the M-bit-per-cell block(s), corrected for errors using a first error correction method, and executed. Data accessed subsequently from the N-bit-per-cell blocks are corrected using an error correction method that corrects more errors per block than the first error correction method.
1. A method for booting a computerized system, the method comprising:
(a) providing a flash memory device that includes a plurality of memory cells grouped into a plurality of blocks, the flash memory device being configured so that at least one of the blocks is operated in a mode in which M bits are stored per cell, and so that remaining blocks of the plurality of blocks are operated in a mode in which N>M bits are stored per cell, where M and N are integral numbers;
(b) upon powering up the computerized system:
(i) retrieving an initialization program for the booting from the at least one of the blocks which is operated in the mode in which only M bits are stored per cell,
(ii) correcting at least one error in the initialization program, using a flash controller's circuitry for correcting bit errors, and
(iii) executing the initialization program; and
(c) upon completing the executing:
(i) accessing data from at least one of the remaining blocks storing N bits per cell, and
(ii) correcting the data accessed from the at least one of the remaining blocks storing N bits per cell, using a software error correction code (ECC) routine of a processor, the software error correction code (ECC) routine corrects more errors per block than the flash controller's circuitry for correcting bit errors, and the processor is integrated with the flash controller and is connected to the flash memory device.
2. The method, according to claim 1 , wherein M equals 1 and N equals 2.
3. The method, according to claim 1 , wherein M equals 1 and N equals 4.
4. The method, according to claim 1 , wherein the at least one of the blocks which is operated in the mode in which only M bits per cell are stored per cell, is one block.
5. The method according to claim 1 , wherein:
the step (c) (ii) is performed by the processor while copying the data from the at least one of the remaining blocks storing N bits per cell to an executable memory connected to the processor.
6. The method according to claim 1 , wherein:
the flash controller is a hardware flash controller embedded in the processor.
7. The method according to claim 1 , further comprising:
in connection with step (b)(ii), detecting the at least one error in the initialization program using error detection coding (EDC) circuitry of the flash controller.
8. A method of operating a computerized system, the method comprising:
(a) providing a flash memory device that includes a plurality of memory cells grouped into a plurality of blocks, the flash memory device is connected to a processor, the processor is integrated with a flash controller, the flash memory device being configured so that at least one of the blocks is operated in a mode in which only M bits are stored per cell, and so that remaining blocks of the plurality of blocks are operated in a mode in which N>M bits are stored per cell, where M and N are integral numbers;
(b) storing, in the at least one of the blocks which is operated in the mode in which only M bits are stored per cell, an initialization program for booting the computerized system;
(c) upon powering up the system, retrieving the initialization program from the at least one of the blocks which is operated in the mode in which only M bits are stored per cell and executing the initialization program;
(d) correcting at least one error in the initialization program, using circuitry for correcting bit errors, the circuitry for correcting bit errors is in the flash controller;
(e) upon completing the executing, accessing data from at least one of the remaining blocks storing N bits per cell; and
(f) correcting errors in the data from the at least one of the remaining blocks storing N bits per cell using a software error correction code routine of the processor that corrects more errors per block than the flash controller's circuitry for correcting bit errors.
9. The method according to claim 8 , wherein:
the step (f) is performed by the processor while copying the data from the at least one of the remaining blocks storing N bits per cell to an executable memory connected to the processor.
10. The method according to claim 8 , wherein:
the flash controller is a hardware flash controller embedded in the processor.
11. The method according to claim 8 , further comprising:
in connection with step (d), detecting the at least one error in the initialization program using error detection coding (EDC) circuitry of the flash controller.
12. A computerized system, comprising:
a flash memory device;
a flash controller for the flash memory device, the flash controller includes circuitry for correcting bit errors; and
a processor which is integrated with the flash controller and which is connected to the flash memory device, the processor includes a software error correction code (ECC) routine;
the flash memory device includes a plurality of memory cells grouped into a plurality of blocks, the flash memory device being configured so that at least one of the blocks is operated in a mode in which only M bits are stored per cell, and so that remaining blocks of the plurality of blocks are operated in a mode in which N>M bits are stored per cell, where M and N are integral numbers;
the flash controller, upon a powering up of the computerized system: (i) retrieves an initialization program for booting from the at least one of the blocks which is operated in the mode in which only M bits are stored per cell, (ii) corrects at least one error in the initialization program using the flash controller's circuitry for correcting bit errors, and (iii) executes the initialization program; and
the processor: (i) accesses data from at least one of the remaining blocks storing N bits per cell, and (ii) corrects the data accessed from the at least one of the remaining blocks storing N bits per cell using the software ECC routine, the software ECC routine corrects more errors per block than the flash controller's circuitry for correcting bit errors.
13. The computerized system according to claim 12 , further comprising:
an executable memory connected to the processor, the processor corrects the data accessed from the at least one of the remaining blocks storing N bits per cell using the software ECC routine while copying the data from the at least one of the remaining blocks storing N bits per cell to the executable memory.
14. The computerized system according to claim 12 , wherein:
the flash controller is a hardware flash controller embedded in the processor.
15. The computerized system according to claim 12 , wherein:
the flash controller detects the at least one error in the initialization program using error detection coding (EDC) circuitry of the flash controller.