Mixed voltage tolerant input/output electrostatic discharge devices

1. An input/output (I/O) mixed-voltage electrostatic discharge protection device for coupling to an I/O pad, the device comprising:

an NFET device having a gate, a drain, a source and body, the gate adapted for coupling to a pre-drive circuit, the source and the body being coupled to one another and to ground;

a bipolar junction transistor having a collector, an emitter and a base, the emitter being coupled to the drain of the NFET and the collector being configured to couple to the I/O pad; and

a resistive element coupled across the collector and emitter.

2. The device of claim 1 , wherein the collector is coupled to the I/O pad.

3. The device of claim 1 , wherein the resistive element is an N-region

4. The device of claim 3 , wherein the NFET device and the bipolar junction transistor are formed in a common P-well.

5. The device of claim 4 , wherein the drain is a formed by an N+ region formed in the P-well and the source is formed by an N+ region formed in the P-well and wherein the source is separated from a body contact region by a shallow trench isolator.

6. The device of claim 5 , wherein the base of the bipolar junction transistor is formed by the P-well, the collector is formed by an N+ region disposed in the P-well, and the emitter is co-formed with the drain.

7. The device of claim 6 , wherein the N-region is disposed between the collector and the emitter.

8. The device of claim 7 , further comprising a silicide blocking layer disposed over the N-region and at least a portion the collector and the emitter.

9. The device of claim 4 , wherein the drain and the emitter are formed by the N-region and the source is formed by an N+ region formed in the P-well and wherein the source is separated from a body contact region by a shallow trench isolator.

10. The device of claim 9 , wherein the collector is formed by an N+ region disposed in the P-well and the N-region and a portion of the collector are covered by a silicide blocking layer.

11. The device of claim 1 , wherein the device includes an isolated p-well and a p-well separated from one another by an N-region, the isolated p-well being separated from a P-substrate by an N-band and N-well regions.

12. The device of claim 11 , wherein the collector is an N+ region formed in the isolated p-well, the emitter is an N+ region formed in both the isolated p-well and the p-well and the isolated p-well is coupled to a biasing voltage via a P+ region formed therein.

13. The device of claim 12 , wherein the drain is a co-formed with the emitter, the source is formed by an N+ region formed in the p-well and the source is separated from a body contact region by a shallow trench isolator.