Double-buffering of video data
View Patent ↗Data is written to one of two frame buffers in write access cycles having write and non-write sub-periods. Data is read out to a display device from the other of the two frame buffers in read access cycles having read and non-read sub-periods. The writing of data and the reading of data are switched to a respective opposite frame buffer during a switching opportunity, a switching opportunity occurring when a read access cycle is in a non-read sub-period and a write access cycle is in a non-write sub-period. A count of the number of times a switching opportunity is not executed because a read access cycle is in a non-read sub-period while a write access cycle is in a write sub-period is incremented. If the count exceeds a particular threshold, a write access cycle subsequent to the count exceeding the threshold is masked. When a write access cycle is a masked data is not written into a buffer.
1. A method comprising:
writing data to one of two frame buffers in write access cycles, each of the write access cycles having a write and a non-write sub-period, and concurrently reading out data to a display device from the other of the two frame buffers in read access cycles, each of the read access cycles having a read and a non-read sub-period, a switching opportunity occurring when a read access cycle is in a non-read sub-period;
executing a buffer switch by switching the writing of data and the reading of data to the respective opposite frame buffer during a switching opportunity while a write access cycle is in a non-write sub-period;
incrementing a count of the number of times a buffer switch is not executed during a switching opportunity because a write access cycle is in a write sub-period; and
if the count exceeds a particular threshold, masking a write access cycle subsequent to the count exceeding the threshold.
2. The method of claim 1 , wherein data is not written during a write access cycle that is masked.
3. The method of claim 1 , wherein a buffer switch is executed during a switching opportunity when a read access cycle is in a portion of a non-read sub-period of a read access cycle and a write access cycle is in a non-write sub-period, the portion being less than the full non-read sub-period.
4. The method of claim 1 , further comprising resetting the count after a buffer switch is executed.
5. The method of claim 1 , wherein the data is compressed video data.
6. The method of claim 1 , wherein the data is pixel format video data.
7. The method of claim 6 , wherein the video data is written according to a progressive scan.
8. The method of claim 6 , wherein the video data is written according to an interlaced scan.
9. The method of claim 6 , wherein the video data is read out according to a progressive scan.
10. The method of claim 6 , wherein the video data is read out according to an interlaced scan.
11. The method of claim 1 , wherein a buffer switch is executed during a switching opportunity if a read access cycle starts a non-read sub-period while a write access cycle is in a non-write sub-period.
12. A display controller to control the writing of data to one of two frame buffers in write access cycles, each of the write access cycles having a write and a non-write sub-period, and the concurrent reading out of data to a display device from the other of the two frame buffers in read access cycles, each of the read access cycles having a read and a non-read sub-period, a switching opportunity occurring when a read access cycle is in a non-read sub-period, the display controller comprising:
a read/write control that:
executes a buffer switch by switching the writing of data and the reading of data to the respective opposite frame buffer during a switching opportunity while a write access cycle is in a non-write sub-period,
increments a count of the number of times a buffer switch is not executed during a switching opportunity because a write access cycle is in a write sub-period, and
masks a write access cycle if the count exceeds a particular threshold, the masked write access cycle being the write cycle subsequent to the count exceeding the threshold.
13. The display controller of claim 12 , wherein the read/write control prevents the writing of data in a write access cycle that is masked.
14. The display controller of claim 12 , wherein a buffer switch is executed during a switching opportunity when a read access cycle is in a portion of a non-read sub-period of a read access cycle and a write access cycle is in a non-write sub-period, the portion being less than the full non-read sub-period.
15. The display controller of claim 12 , wherein the read/write control resets the count after a buffer switch is executed.
16. The display controller of claim 12 , wherein the data is compressed video data.
17. The display controller of claim 12 , wherein the read/write control executes a buffer switch during a switching opportunity if a read access cycle starts a non-read sub-period while a write access cycle is in a non-write sub-period.
18. A system to display video data, comprising:
a video source;
a memory having two frame buffers;
a display device; and
a display controller to control the writing of data to one of the frame buffers in write access cycles, each of the write access cycles having a write and a non-write sub-period, and the concurrent reading out of data to a display device from the other of the two frame buffers in read access cycles, each of the read access cycles having a read and a non-read sub-period, a switching opportunity occurring when a read access cycle is in a non-read sub-period, the display controller including a read/write control that:
executes a buffer switch by switching the writing of data and the reading of data to the respective opposite frame buffer during a switching opportunity while a write access cycle is in a non-write sub-period,
increments a count of the number of times a buffer switch is not executed during a switching opportunity because a write access cycle is in a write sub-period, and
masks a write access cycle if the count exceeds a particular threshold, the masked write access cycle being the write cycle subsequent to the count exceeding the threshold.
19. The system of claim 18 , wherein the read/write control prevents the writing of data in a write access cycle that is masked.
20. The system of claim 18 , wherein a buffer switch is executed during a switching opportunity when a read access cycle is in a portion of a non-read sub-period of a read access cycle and a write access cycle is in a non-write sub-period, the portion being less than the full non-read sub-period.
21. The system of claim 18 , wherein the read/write control resets the count after a buffer switch is executed.
22. The display controller of claim 16 , wherein the data is pixel format video data.
23. The system of claim 18 , wherein the read/write control executes a buffer switch during a switching opportunity if a read access cycle starts a non-read sub-period while a write access cycle is in a non-write sub-period.