IP Library Granted Patent US 7,676,716
Granted Patent B2
US 7,676,716 · App. 12/169,216 · Granted Mar 9, 2010

Testable tristate bus keeper

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Quick Facts
Patent No.
US 7,676,716
App. No.
12/169,216
Granted
Mar 9, 2010
Kind
B2
Abstract

A method of testing a tristate element by applying a given value to the tristate, applying an opposite value to a keeper element connected at an output of the tristate, capturing a first value at a downstream position of the tristate, evaluating a second value at the output of the tristate using the first value, comparing the second value to the opposite value, and producing a failure code for the tristate when the second value is not equal to the opposite value. Then, applying the opposite value to the tristate, applying the given value to the keeper element, capturing the first value, evaluating the second value using the first value, comparing the second value to the given value, and producing a failure code for the tristate when the second value is not equal to the given value. A passing code for the tristate is produced when a failure code has not been produced.

Claims (35)

1. A method of testing a tristate capability of a tristate element, the method comprising the steps of:

applying a given logical value to an input of the tristate element,

applying an opposite of the given logical value to a keeper element that is connected at an output of the tristate element,

capturing a first logical value with a latch at a downstream position of the output of the tristate element,

evaluating a second logical value at the output of the tristate element using the first logical value,

comparing the second logical value to the opposite of the given logical value,

producing a failure code for the tristate element when the second logical value is not equal to the opposite of the given logical value,

applying the opposite of the given logical value to the input of the tristate element,

applying the given logical value to the keeper element,

capturing the first logical value with the latch,

evaluating the second logical value at the output of the tristate element using the first logical value,

comparing the second logical value to the given logical value,

producing a failure code for the tristate element when the second logical value is not equal to the given logical value, and

producing a passing code for the tristate element when a failure code has not been produced.

2. A method of testing a tristate capability of a tristate element, the method comprising the steps of:

applying a given logical value to an input of the tristate element,

applying an opposite of the given logical value to a keeper element that is connected at an output of the tristate element,

capturing a first logical value at an output of the keeper element,

comparing the first logical value to the opposite of the given logical value,

producing a failure code for the tristate element when the first logical value is not equal to the opposite of the given logical value,

applying the opposite of the given logical value to the input of the tristate element,

applying the given logical value to the keeper element,

capturing the first logical value at the output of the keeper element,

comparing the first logical value to the given logical value,

producing a failure code for the tristate element when the first logical value is not equal to the given logical value, and

producing a passing code for the tristate element when a failure code has not been produced.

3. A method of determining a failure mode of a chain of tristate elements, the method comprising the steps of:

applying a given logical value to inputs of the tristate elements,

applying an opposite of the given logical value to a keeper element that is connected at an output of the chain of tristate elements,

capturing a first logical value at an output of the keeper element,

comparing the first logical value to the opposite of the given logical value,

producing a failure code for the chain of tristate elements when the first logical value is not equal to the opposite of the given logical value,

loading different patterns of logical values into the inputs of the tristate elements to determine which of the different patterns produce failure codes, and

determining which of the tristate elements are faulty based at least in part upon the different patterns that produce the failure codes.

4. A keeper element for use in testing a tristate element, the keeper element comprising a master loop of feedback inverters, a slave loop of feedback inverters, and a keeper loop of feedback inverters, with one passgate disposed between the keeper loop and the slave loop, one passgate disposed between the slave loop and the master loop, and one passgate disposed upstream of the master loop, where the master loop, slave loop, and keeper loop are all weak relative to the passgates, in that a logical value asserted onto any one of the master loop, slave loop, and keeper loop is overwritable by a logical value asserted by a respective one of the passgates, and where a logical value initially propagated from the master loop and the slave loop to the keeper loop is overwritable upon assertion from another source of a differing logical value.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER PREVIOUSLY RECORDED AT REEL: 047195 FRAME: 0827. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Nov 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047924/0571 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047195/0827 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 8, 2008
From: BROWN, JEFFREY S.; TURNER, MARK F.; MARASCH, MAREK J.
To: LSI CORPORATION
Reel/Frame 021206/0517 →