Verifying data integrity of a non-volatile memory system during data caching process
View Patent ↗To ensure integrity of non-volatile flash, the controller programs the non-volatile memories with background test patterns and verifies the non-volatile memories during power on self test (POST) operation. In conjunction with verifying the non-volatile memories, the controller may routinely run diagnostics and report status to the storage controller. As part of the storage controller power up routines, the storage controller issues a POST command to the controller via an I 2 C register that is monitored by the storage controller. The storage controller may determine that the non-volatile flash is functional without any defects, and the controller may remove power from the non-volatile flash to extend its reliability. Periodically, in the background, the controller may run diagnostic routines to detect any failures associated with the volatile memory and the controller itself.
1. A computer program product comprising a computer recordable medium having a computer readable program recorded thereon, wherein the computer readable program, when executed on a memory system controller, causes the memory system controller to:
responsive to powering on a storage controller, wherein the storage controller comprises a volatile memory and a non-volatile memory, the volatile memory stores cache data for input/output operations performed by the storage controller, and the non-volatile memory hardens cache data from the volatile memory responsive to a power event, and concurrent with the storage controller performing input/output operations using the volatile memory, verify the non-volatile memory, wherein verifying the non-volatile memory comprises:
programming the non-volatile memory with a set of test patterns;
reading the set of test patterns from the non-volatile memory;
verifying whether the non-volatile memory stored the set of test patterns correctly; and
posting a failure status to the storage controller responsive to the non-volatile memory storing the set of test patterns incorrectly.
2. The computer program product of claim 1 , wherein the computer readable program further causes the computing device to:
run background diagnostics concurrent with the storage controller performing input/output operations.
3. The computer program product of claim 2 , wherein running background diagnostics comprises:
snooping an access to the volatile memory system;
responsive to the access being a cache read, directing read data to internal buffer locations of a non-volatile memory controller; and
validating error correction code information in the non-volatile memory controller to validate the internal data pathing within the non-volatile memory controller.
4. The computer program product of claim 2 , wherein running background diagnostics comprises:
responsive to the storage controller writing to the volatile memory, reading the written data from the volatile memory; and
determining whether a fault exists in the written data.
5. The computer program product of claim 2 , wherein running background diagnostics comprises:
incrementing a programming cycles counter responsive to verifying whether the non-volatile memory stored the set of test patterns correctly; and
switching to an alternate background diagnostic routine responsive to the programming cycles counter reaching a predetermined value.
6. The computer program product of claim 5 , wherein the alternate background diagnostic routine comprises:
sending write commands to the non-volatile memory;
verifying that the write commands are acknowledged; and
reading vendor identification information from the non-volatile memory.
7. The computer program product of claim 1 , wherein verifying the non-volatile memory further comprises:
performing a bulk erase to the non-volatile memory responsive to the non-volatile memory storing the set of test patterns correctly; and
sending a command to the storage controller to confirm that the non-volatile memory is pre-programmed.
8. The computer program product of claim 7 , wherein verifying the non-volatile memory further comprises:
responsive to sending the command to the storage controller, power down the non-volatile memory.
9. The computer program product of claim 1 , wherein posting a failure status to the storage controller comprises:
posting a status code in an inter-integrated circuit interface register that is monitored by the storage controller.
10. A method, in a memory system, for verifying data integrity of a non-volatile memory system during data caching process, the method comprising:
responsive to powering on a storage controller, wherein the storage controller comprises a volatile memory and a non-volatile memory, the volatile memory stores cache data for input/output operations performed by the storage controller, and the non-volatile memory hardens cache data from the volatile memory responsive to a power event, and concurrent with the storage controller performing input/output operations using the volatile memory, verify, by a memory system controller in the memory system, the non-volatile memory, wherein verifying the non-volatile memory comprises:
programming a non-volatile memory with a set of test patterns;
reading the set of test patterns from the non-volatile memory;
verifying whether the non-volatile memory stored the set of test patterns correctly; and
posting a failure status to the storage controller responsive to the non-volatile memory storing the set of test patterns incorrectly.
11. The method of claim 10 , further comprising:
running, by the memory system controller, background diagnostics concurrent with the storage controller performing input/output operations.
12. The method of claim 11 , wherein running background diagnostics comprises:
snooping an access to the volatile memory system;
responsive to the access being a cache read, directing read data to internal buffer locations of a non-volatile memory controller; and
validating error correction code information in the non-volatile memory controller, to validate the internal data pathing within the non-volatile memory controller.
13. The method of claim 11 , wherein running background diagnostics comprises:
responsive to the storage controller writing to the volatile memory, reading the written data from the volatile memory; and
determining whether a fault exists in the written data.
14. The method of claim 11 , wherein running background diagnostics comprises:
incrementing a programming cycles counter responsive to verifying whether the non-volatile memory stored the set of test patterns correctly; and
switching to an alternate background diagnostic routine responsive to the programming cycles counter reaching a predetermined value.
15. The method of claim 14 , wherein the alternate background diagnostic routine comprises:
sending write commands to the non-volatile memory;
verifying that the write commands are acknowledged; and
reading vendor identification information from the non-volatile memory.
16. The method of claim 10 , wherein verifying the non-volatile memory further comprises:
performing a bulk erase to the non-volatile memory responsive to the non-volatile memory storing the set of test patterns correctly;
sending a command to the storage controller to confirm that the non-volatile memory is pre-programmed; and
powering down the non-volatile memory.
17. The method of claim 10 , wherein posting a failure status to the storage controller comprises:
posting, by the memory system controller, a status code in an inter-integrated circuit interface register that is monitored by the storage controller.
18. A memory system comprising:
a controller, wherein the controller detects a power event from a power supply that provides power to a storage controller and the memory system;
a volatile memory, wherein the volatile memory stores cache data for input/output operations performed by a storage controller; and
a non-volatile memory, wherein the controller hardens the cache data from the volatile memory for the storage controller to the non-volatile memory responsive to the power event;
wherein responsive to powering on the storage controller and concurrent with the storage controller performing input/output operations using the volatile memory, the controller verifies the non-volatile memory, wherein verifying the non-volatile memory comprises:
programming the non-volatile memory with a set of test patterns;
reading the set of test patterns from the non-volatile memory;
verifying whether the non-volatile memory stored the set of test patterns correctly; and
posting a failure status to the storage controller responsive to the non-volatile memory storing the set of test patterns incorrectly.
19. The memory system of claim 18 , wherein the controller runs background diagnostics concurrent with the storage controller performing input/output operations.
20. The memory system of claim 18 , wherein the controller posts the failure status to the storage controller in an inter-integrated circuit interface register that is monitored by the storage controller.