Thin film transistor and method of manufacturing the same

1. A thin film transistor comprising:

first and second ohmic contact layers formed on an insulating substrate;

an activation layer formed on the insulating substrate and the first and second ohmic contact layers;

an insulating layer formed on the activation layer;

a source electrode formed on the insulating layer and electrically connected to the first ohmic contact layer through a first contact hole, the first contact hole extending through the activation layer and the insulating layer to the first ohmic contact layer;

a drain electrode formed on the insulating layer and electrically connected to the second ohmic contact layer through a second contact hole, the second contact hole extending through the activation layer and the insulating layer to the second ohmic contact layer;

a gate electrode formed on the insulating layer between the source electrode and the drain electrode and overlapping the activation layer; and

a protective layer formed on the source electrode, the drain electrode, and the gate electrode.

2. The thin film transistor of claim 1 , wherein the source electrode, the drain electrode, and the gate electrode are formed from substantially the same layer.

3. The thin film transistor of claim 1 , wherein the protective layer has a third contact hole extending to the drain electrode so that the drain electrode is electrically connected to a pixel electrode.

4. The thin film transistor of claim 1 , wherein a distance between the source electrode and the gate electrode ranges from about 1 μm to about 20 μm.

5. The thin film transistor of claim 1 , wherein a distance between the drain electrode and the gate electrode ranges from about 1 μm to about 20 μm.

6. The thin film transistor of claim 1 , wherein a distance between an end of the gate electrode and an end of each of the first and second ohmic contact layers ranges from about −4 μm to about 20 μm, the negative sign in the distance indicating that the gate electrode overlaps the first or second ohmic contact layer, and wherein the distance is measured in a direction that is parallel to a surface of the insulating substrate on which the activation layer is formed.

7. The thin film transistor of claim 1 , wherein the activation layer comprises crystalline silicon or amorphous silicon.

8. The thin film transistor of claim 1 , wherein the insulating layer comprises silicon oxide (SiOx) or silicon nitride (SiNx).

9. The thin film transistor of claim 1 , wherein the source electrode, the drain electrode, and the gate electrode are formed of a conductive metal.

10. The thin film transistor of claim 1 , wherein the protective layer comprises silicon oxide (SiOx) or silicon nitride (SiNx).

11. A method of manufacturing a thin film transistor, comprising:

forming first and second ohmic contact layers on an insulating substrate;

forming an activation layer on the insulating substrate, and the first and second ohmic contact layers;

forming an insulating layer on the activation layer;

forming first and second contact holes, that extend through the activation layer and the insulating layer to the first and second ohmic contact layers, respectively;

forming a metal layer on the insulating layer to be electrically connected to the first and second ohmic contact layers;

patterning the metal layer to form a gate electrode, and a source electrode and a drain electrode spaced from the gate electrode; and

forming a protective layer on the source electrode, the drain electrode, and the gate electrode.

12. The method of claim 11 , further comprising:

forming a third contact hole extending to the drain electrode, the third contact hole extending through the protective layer.

13. The method of claim 11 , wherein a distance between the source electrode and the gate electrode ranges from about 1 μm to about 20 μm.

14. The method of claim 11 , wherein a distance between the drain electrode and the gate electrode ranges from about 1 μm to about 20 μm.

15. The method of claim 11 , wherein a distance between an end of the gate electrode and an end of each of the first and second ohmic contact layers ranges from about −4 μm to about 20 μm, the negative sign in the distance indicating that the gate electrode overlaps the first or second ohmic contact layer, and wherein the distance is measured in a direction that is parallel to a surface of the insulating substrate on which the activation layer is formed.

16. The method of claim 11 , wherein the activation layer comprises crystalline silicon or amorphous silicon.

17. The method of claim 11 , wherein the insulating layer comprises silicon oxide (SiOx) or silicon nitride (SiNx).

18. The method of claim 11 , wherein the insulating layer comprises silicon oxide (SiOx) or silicon nitride (SiNx).

19. An organic light emitting diode (OLED) device comprising a thin film transistor, wherein the thin film transistor comprises:

first and second ohmic contact layers formed on an insulating substrate;

an activation layer formed on the insulating substrate and the first and second ohmic contact layers;

an insulating layer formed on the activation layer;

a source electrode formed on the insulating layer and electrically connected to the first ohmic contact layer through a first contact hole, the first contact hole extending through the activation layer and the insulating layer to the first ohmic contact layer;

a drain electrode formed on the insulating layer and electrically connected to the second ohmic contact layer through a second contact hole, the second contact hole extending through the activation layer and the insulating layer to the second ohmic contact layer;

a gate electrode formed on the insulating layer between the source electrode and the drain electrode and overlapping the activation layer; and

a protective layer formed on the source electrode, the drain electrode, and the gate electrode.