Circuit with single-ended input and differential output

1. An integrated circuit comprising:

a single-ended input node;

a first differential output node;

a second differential output node;

an inverting stage coupled between the single-ended input node and the first differential output node, the inverting stage comprising at least one transistor with a first current terminal, a second current terminal, and a control terminal, the first current terminal being coupled to the first differential output node, and the control terminal being coupled to the single-ended input node; and

a non-inverting stage coupled between the single-ended input node and the second differential output node, the non-inverting stage comprising at least one transistor with a first current terminal, a second current terminal, and a control terminal, the first current terminal being coupled to the second differential output node, and the second current terminal being coupled to the single-ended input node;

wherein a bias current of the inverting stage is larger than a bias current of the non-inverting stage.

2. The integrated circuit according to claim 1 ,

wherein the at least one transistor of the inverting stage is a field-effect transistor in common-source configuration, and

wherein the at least one transistor of the non-inverting stage is a field-effect transistor in common-gate configuration.

3. The integrated circuit according to claim 1 , comprising:

a bias circuit configured to set the bias current of the inverting stage and the bias current of the non-inverting stage.

4. The integrated circuit according to claim 3 , wherein the bias circuit comprises a bias voltage source coupled to the control terminal of the at least one transistor of the non-inverting stage.

5. The integrated circuit according to claim 3 ,

wherein the bias circuit comprises an operational amplifier with a non-inverting differential input, an inverting differential input, and a single-ended output,

wherein the non-inverting differential input is coupled to the inverting stage,

wherein the inverting differential input is coupled to the non-inverting stage, and

wherein the single-ended output is coupled to the control terminal of the at least one transistor of the non-inverting stage.

6. The integrated circuit according to claim 3 ,

wherein the bias circuit comprises a replica circuit of the inverting stage and a replica circuit of the non-inverting stage,

wherein the bias voltage source comprises an operational amplifier with a non-inverting differential input, an inverting differential input, and a single-ended output,

wherein the non-inverting differential input is coupled to the replica circuit of the inverting stage,

wherein the inverting differential input is coupled to the replica circuit of the non-inverting stage, and

wherein the single-ended output is coupled to the control terminal of the at least one transistor of the non-inverting stage.

7. The integrated circuit according to claim 3 , wherein the bias circuit comprises a bias current source coupled in series with the at least one transistor of the non-inverting amplifier stage.

8. The integrated circuit according to claim 1 , wherein a transistor channel length of the inverting stage is different from a transistor channel length of the non-inverting stage.

9. The integrated circuit according to claim 8 ,

wherein the inverting stage comprises a first number of transistors connected in series,

wherein the non-inverting stage comprises a second number of transistors connected in series, and

wherein the first number is different from the second number.

10. The integrated circuit according to claim 1 , wherein a transistor channel width of the inverting stage is different from a transistor channel width of the non-inverting stage.

11. The integrated circuit according to claim 10 ,

wherein the inverting stage comprises a first number of transistors connected in parallel,

wherein the non-inverting stage comprises a second number of transistors connected in parallel, and

wherein the first number is different from the second number.

12. The integrated circuit according to claim 1 ,

wherein the inverting stage comprises at least one resistor coupled to the first differential output node, and

wherein the non-inverting stage comprises at least one resistor coupled to the second differential output node.

13. The integrated circuit according to claim 12 , wherein the resistance of the at least one resistor of the non-inverting stage is larger than the resistance of the at least one resistor of the inverting stage.

14. An integrated circuit comprising:

a single-ended input node;

a first differential output node;

a second differential output node;

an inverting stage coupled between the single-ended input node and the first differential output node, the inverting stage comprising at least one transistor with a first current terminal, a second current terminal and a control terminal, the first current terminal being coupled to the first differential output node, and the control terminal being coupled to the single-ended input node; and

a non-inverting stage coupled between the single-ended input node and the second differential output node, the non-inverting stage comprising at least one transistor with a first current terminal, a second current terminal, and a control terminal, the first current terminal being coupled to the second differential output node, and the second current terminal being coupled to the single-ended input node;

wherein a transistor geometry of the inverting stage is different from a transistor geometry of the non-inverting stage;

wherein a transistor channel length of the inverting stage is different from a transistor channel length of the non-inverting stage

wherein the inverting stage comprises a first number of transistors connected in series,

wherein the non-inverting stage comprises a second number of transistors connected in series, and

wherein the first number is different from the second number.

15. The integrated circuit according to claim 14 ,

wherein the at least one transistor of the inverting stage is a field-effect transistor in common-source configuration and

wherein the at least one transistor of the non-inverting stage is a field-effect transistor in common-gate configuration.

16. A method, comprising:

applying a single-ended input signal to a control terminal of a first transistor,

applying the single-ended input signal to a current output terminal of a second transistor,

tapping a first inverted differential output signal at a current input terminal of the first transistor, tapping a second non-inverted differential output signal at a current input terminal of the second transistor, and

setting a bias current of the first transistor to be larger than a bias current of the second transistor.

17. The method according to claim 16 ,

wherein the first transistor is a field-effect transistor in common-source configuration, and

wherein the second transistor is a field-effect transistor in common-gate configuration.

18. The method according to claim 16 , further comprising:

providing the first transistor with a transistor channel length different from the second transistor.

19. The method according to claim 16 , further comprising:

providing the first transistor with a transistor channel width different from the second transistor.

20. An electronic device, comprising a single-ended to differential converter, wherein the single-ended to differential converter comprises:

a single-ended input;

a first differential output;

a second differential output;

an inverting stage coupled between the single-ended input and a first differential output, the inverting stage comprising at least one transistor with a first current terminal, a second current terminal, and a control terminal, the first current terminal being coupled to the first differential output, and the control terminal being coupled to the single-ended input; and

a non-inverting stage coupled between the single-ended input and the second differential output, the non-inverting stage comprising at least one transistor with a first current terminal, a second current terminal, and a control terminal, the first current terminal being coupled to the second differential output, the second current terminal being coupled to the single-ended input;

wherein a bias current of the inverting stage is larger than a bias current of the non-inverting stage.

21. The electronic device according to claim 20 , wherein a transistor geometry of the inverting stage is different from a transistor geometry of the non-inverting stage.

22. An integrated circuit comprising:

a single-ended input node;

a first differential output node;

a second differential output node;

an inverting stage coupled between the single-ended input node and the first differential output node, the inverting stage comprising at least one transistor with a first current terminal, a second current terminal and a control terminal, the first current terminal being coupled to the first differential output node, and the control terminal being coupled to the single-ended input node; and

a non-inverting stage coupled between the single-ended input node and the second differential output node, the non-inverting stage comprising at least one transistor with a first current terminal, a second current terminal, and a control terminal, the first current terminal being coupled to the second differential output node, and the second current terminal being coupled to the single-ended input node;

wherein a transistor geometry of the inverting stage is different from a transistor geometry of the non-inverting stage;

wherein a transistor channel width of the inverting stage is different from a transistor channel width of the non-inverting stage;

wherein the inverting stage comprises a first number of transistors connected in parallel,

wherein the non-inverting stage comprises a second number of transistors connected in parallel, and

wherein the first number is different from the second number.