Semiconductor memory device having error correction function

1. A semiconductor memory device which stores predetermined code words each composed of information bits and parity check bits, comprising:

a memory cell array having a plurality of word lines and a plurality of bit lines and having a plurality of memory cells respectively formed at places at which said word lines and said bit lines cross over, said memory cells being arranged in a matrix;

a row decoder to select one of said word lines based on a row address signal;

a column decoder to select some of said bit lines based on a column address signal;

an error correction circuit to perform error correction on a code word read through the bit lines selected by said column decoder from ones of said memory cells located at places at which the word line selected by said row decoder and the selected bit lines cross over, thereby detecting an error position in the code word to generate error detection data indicating said error position, and to correct the information bit in said detected error position to generate error corrected data; and

an output circuit to receive said error detection data and said error corrected data from said error correction circuit,

wherein said output circuit relays said error corrected data to outside when a normal operation mode has been designated and relays said error detection data to outside when a test operation mode has been designated.

2. A semiconductor memory device according to claim 1 , further comprising:

a test control circuit to supply a control signal indicating either said test operation mode or said normal operation mode to said output circuit,

wherein said output circuit outputs said error corrected data when said control signal indicates said normal operation mode and outputs said error detection data instead of said error corrected data when said control signal indicates said test operation mode.

3. A semiconductor memory device according to claim 1 , wherein when a code word of one page size has been read in bitwise parallel from said memory cell array in a page access mode, said output circuit time divides said error corrected data generated in said error correction circuit sequentially into multiple time divided error corrected data according to an input page address to output consecutively said multiple time divided error corrected data.

4. A semiconductor memory device according to claim 2 , wherein when a code word of one page size has been read in bitwise parallel from said memory cell array in a page access mode, said output circuit time divides said error corrected data generated in said error correction circuit sequentially into multiple time divided error corrected data according to an input page address to output consecutively said multiple time divided error corrected data.

5. A semiconductor memory device according to claim 2 , wherein said output circuit comprises:

a selecting circuit to select data from among said error corrected data according to an input page address; and

an output buffer circuit to output error corrected data selected by said selecting circuit when said normal operation mode has been designated and to output said error detection data supplied from said error correction circuit when said test operation mode has been designated; and

wherein said output buffer circuit comprises a selector to select either said error detection data supplied from said error correction circuit or the error corrected data selected by said selecting circuit and to output the selected data.

6. A semiconductor memory device according to claim 5 , wherein said output buffer circuit comprises delay elements to delay said error detection data.

7. A semiconductor memory device according to claim 2 , wherein said output circuit comprises:

a selecting circuit to select data from among said error corrected data according to an input page address and to select either the selected data or said error detection data supplied from said error correction circuit; and

an output buffer circuit to relay the data selected by said selecting circuit to outside, and

wherein said selecting circuit comprises a selector to select the data selected by said selecting circuit according to said input page address when said normal operation mode has been designated and to select said error detection data supplied from said error correction circuit when said test operation mode has been designated.

8. A semiconductor memory device according to claim 7 , wherein said selecting circuit comprises delay elements to delay said error detection data.

9. A semiconductor memory device according to claim 1 , wherein each said memory cell is constituted by a nonvolatile memory element.

10. A semiconductor memory device according to claim 2 , wherein each said memory cell is constituted by a nonvolatile memory element.

11. A semiconductor memory device according to claim 3 , wherein each said memory cell is constituted by a nonvolatile memory element.

12. A semiconductor memory device according to claim 4 , wherein each said memory cell is constituted by a nonvolatile memory element.

13. A semiconductor memory device according to claim 5 , wherein each said memory cell is constituted by a nonvolatile memory element.

14. A semiconductor memory device according to claim 6 , wherein each said memory cell is constituted by a nonvolatile memory element.

15. A semiconductor memory device according to claim 7 , wherein each said memory cell is constituted by a nonvolatile memory element.

16. A semiconductor memory device according to claim 8 , wherein each said memory cell is constituted by a nonvolatile memory element.