Semiconductor integrated circuit
View Patent ↗A semiconductor integrated circuit having a test circuit for inspecting states of connections between a plurality of pads and respective external terminals by bonding wires. The test circuit comprises, for each of a plurality of pads, a control terminal provided to receive a control signal of a logic level equal to the logic level of a signal applied to a corresponding one of the external terminals, an inverter which inverts the logic level on the control terminal, an inverted output terminal of the inverter being connected to the pad via a connection line; and an exclusive-NOR gate which outputs an exclusive NOR of the logic level on the connection line and the logic level on the control terminal.
1. A semiconductor integrated circuit having a plurality of pads to be connected by bonding wires to respective external terminals so that logic levels of signals applied to said external terminals are given to said plurality of pads, and a test circuit for inspecting states of connections between said plurality of pads and said respective external terminals, wherein
said test circuit comprises: for each of said plurality of pads,
a control terminal provided to receive a control signal of a logic level equal to the logic level of a signal applied to a corresponding one of said external terminals;
an inverter which inverts the logic level on said control terminal, an inverted output terminal of said inverter being connected to the pad via a connection line; and
an exclusive-NOR gate which is separately connected to said connection line and said control terminal, and outputs an exclusive NOR of the logic level on said connection line and the logic level on said control terminal, and
wherein an output of the exclusive NOR indicates a test result of the connection state between the pad and the corresponding external terminal.
2. The semiconductor integrated circuit according to claim 1 , wherein said test circuit further comprises a NAND circuit which produces an inverted value of a logical product of the outputs of the respective exclusive-NOR gates for said plurality of pads.
3. The semiconductor integrated circuit according to claim 1 , wherein when the logic level on said control terminal and the logic level on the pad are equal, said inverter operates so that the logic level on said connection line becomes equal to the logic level on the pad.
4. The semiconductor integrated circuit according to claim 1 , wherein when the connection state between the pad and the corresponding external terminal is a normal state, a logic level of said connection line is different from a output level of said inverter and said exclusive-NOR gate produces a high level output.
5. The semiconductor integrated circuit according to claim 1 , wherein when the connection state between the pad and the corresponding external terminal is an open state, a logic level of said connection line is equal to a output level of said inverter and said exclusive-NOR gate produces a low level output.
6. The semiconductor integrated circuit according to claim 1 , wherein when the connection state between the pad and the corresponding external terminal is a shorted state, a logic level of said connection line is equal to a output level of said inverter and said exclusive-NOR gate produces a low level output.