DATA READING METHOD FOR SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE
The present invention provides a data reading method suitable for use in a semiconductor memory device equipped with a plurality of semiconductor memory chips, which is capable of suppressing an increase in layout area as compared with a required storage capacity, and a semiconductor memory device. Two memory chips are sequentially selected in the way of combinations different from each other from within a plurality of memory chips each having a first storage area and a second storage area. Data are simultaneously read from the first storage area of one of the selected two memory chips and the second storage area of the other thereof.
1 . A data reading method suitable for use in a semiconductor memory device equipped with n (where n: positive integer) memory chips respectively having first and second storage areas, comprising the steps of:
sequentially selecting two memory chips in the way of combinations different from each other from within the n memory chips; and
reading data simultaneously from the first storage area of one of the two memory chips and the second storage area of the other thereof both selected by said chip selecting step.
2 . The data reading method according to claim 1 , wherein said n is odd.
3 . The data reading method according to claim 1 , wherein the first storage area is an area that belongs to each address lower than a predetermined address in a full storage area of each of the memory chips, and the second storage area is an area that belongs to each address higher than the predetermined address.
4 . A data reading method suitable for use in a semiconductor memory device equipped with first through third memory chips respectively having first and second storage areas, comprising the steps:
a first step for simultaneously reading data from the first storage area of the first memory chip and the second storage area of the second memory chip;
a second step for simultaneously reading data from the second storage area of the third memory chip and the first storage area of the second memory chip; and
a third step for simultaneously reading data from the second storage area of the first memory chip and the first storage area of the third memory chip.
5 . The data reading method according to claim 4 , wherein the first storage area is an area that belongs to each address lower than a predetermined address in a full storage area of each of the first through third memory chips, and the second storage area is an area that belongs to each address higher than the predetermined address.
6 . A semiconductor memory device comprising:
n (where n: positive integer) memory chips mounted therein, which respectively read data stored at addresses indicated by common address data according to the common address data,
wherein each of the memory chips includes:
a memory module having a first storage area and a second storage area, and
storage area switching means for switching one storage area to be targeted for reading according to the address data within the first and second storage areas to the other storage area according to a chip set bit.
7 . The semiconductor memory device according to claim 6 , wherein said n is odd.
8 . The semiconductor memory device according to claim 6 , wherein the first storage area is an area that belongs to each address lower than a predetermined address in a full storage area of each of the memory chips, and the second storage area is an area that belongs to each address higher than the predetermined address.