Thin film transistor substrate
View Patent ↗A thin film transistor array panel comprises a plurality of gate lines formed on an insulating substrate; a repair line formed on the insulating substrate; a gate insulating layer formed on the gate lines and the repair line; a plurality of data lines formed on the gate insulating layer; an electricity dissipation line formed on the gate insulating layer crossing the gate lines and the repair line; and a first diode connecting the repair line and the electricity dissipation line. When static electricity is introduced through the repair lines, the static electricity is transferred to the electricity dissipation line and is dispersed or exhausted before it reaches to the data lines. As a result, the TFTs and wires in the display area are prevented from being destroyed by the static electricity.
1. A thin film transistor array panel comprising:
an insulating substrate comprising a display area;
a first signal line disposed on the insulating substrate;
a second signal line crossing the first signal line, and insulated from the first signal line;
a repair line disposed outside the display area, and configured to allow laser shorting with the second signal line for repair;
an electricity dissipation line disposed outside the display area and crossing the first signal line and the repair line, respectively; and
a first diode connected directly to the repair line and the electricity dissipation line, and configured to have polarity such that current flows from the repair line to the electricity dissipation line.
2. The thin film transistor array panel of claim 1 , wherein the first diode comprises:
first gate and drain electrodes electrically connected to the repair line, a first source electrode electrically connected to the electricity dissipation line, and a first semiconductor overlapping the first gate electrode and contacting the first source and drain electrodes.
3. The thin film transistor array panel of claim 2 , further comprising a second diode connected to the first signal line and the electricity dissipation line, respectively, and configured to have polarity such that current flows from the first signal line to the electricity dissipation line.
4. The thin film transistor array panel of claim 3 , further comprising a third diode connected to the first signal line and the electricity dissipation line, respectively, and configured to have polarity such that current flows from the electricity dissipation line to the first signal line.
5. The thin film transistor array panel of claim 1 , further comprising:
a second diode connected directly to the repair line and the electricity dissipation line, and configured to have polarity such that current flows from the repair line to the electricity dissipation line.
6. A thin film transistor array panel comprising:
an insulating substrate comprising a display area;
a first signal line disposed on the insulating substrate;
a second signal line crossing the first signal line, and insulated from the first signal line;
a repair line disposed outside the display area, and configured to allow laser shorting with the second signal line for repair, the repair line being disposed on the same layer as the first signal line;
an electricity dissipation line disposed outside the display area and crossing the first signal line and the repair line, respectively, the electricity dissipation line disposed on the same layer as the second signal line; and
a first diode connected directly to the repair line and the electricity dissipation line, and configured to have polarity such that current flows from the repair line to the electricity dissipation line.
7. The thin film transistor array panel of claim 6 , wherein the first diode comprises:
a first gate electrode disposed on the insulating substrate and electrically connected to the repair line;
a semiconductor layer insulated from the gate electrode and overlapping the gate electrode; and
first source and drain electrodes separated from each other and each contacting the semiconductor layer, the first drain electrode electrically connected to the repair line.
8. The thin film transistor array panel of claim 7 , further comprising:
a first insulating layer covering the gate electrode and the repair line;
a second insulating layer covering the semiconductor layer and the first source and drain electrodes; and
a connector electrically connecting the repair line and the first drain electrode through contact holes formed in the first and second insulating layers.
9. The thin film transistor array panel of claim 7 , further comprising a second diode connected to the first signal line and the electricity dissipation line, respectively, and configured to have polarity such that current flows from the first signal line to the electricity dissipation line.
10. The thin film transistor array panel of claim 9 , further comprising a third diode connected to the first signal line and the electricity dissipation line, respectively, and configured to have polarity such that current flows from the electricity dissipation line to the first signal line.
11. The thin film transistor array panel of claim 10 , further comprising a fourth diode connected directly to the repair line and the electricity dissipation line, and configured to have polarity such that current flows from the repair line to the electricity dissipation line.