IP Library Granted Patent US 8,716,142
Granted Patent B2
US 8,716,142 · App. 12/178,316 · Granted May 6, 2014

Semiconductor device and method of manufacturing the same

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Quick Facts
Patent No.
US 8,716,142
App. No.
12/178,316
Granted
May 6, 2014
Kind
B2
Abstract

Provided is a semiconductor device formed with a trench portion for providing a concave portion in a gate width direction and with a gate electrode provided within and on a top surface of the trench portion via a gate insulating film. At least a part of a surface of each of the source region and the drain region is made lower than other parts of the surface by removing a thick oxide film formed in the vicinity of the gate electrode. Making lower the part of the surface of each of the source region and the drain region allows current flowing through a top surface of the concave portion of the gate electrode at high concentration to flow uniformly through the entire trench portion, which increase an effective gate width of the concave portion formed so as to have a varying depth in a gate width direction.

Claims (20)

1. A method of manufacturing a semiconductor device, comprising:

preparing a semiconductor substrate of a first conductivity type;

removing a portion from a surface of the semiconductor substrate to form a concave surface region;

forming trenches having a side surface and a bottom surface in a region to become a channel, such that the semiconductor substrate surface has a planar portion and trench portions, wherein the trenches are spaced away from the concave surface region along the surface by a constant distance, such that the concave surface region follows a contour of the side surface of the trenches;

forming a gate insulating film on the side surface and the bottom surface of the trenches and on the surface of the planar portion;

forming a gate electrode on the gate insulating film, such that the gate electrode extends farther in a channel length direction in the trench portions than in the planar portion; and

forming a source region of a second conductivity type and a drain region of the second conductivity type in the substrate below the concave surface region, such that the source and drain regions are adjacent to the side surfaces of the trenches and sandwich the gate electrode therebetween below the concave surface region.

2. A method of manufacturing a semiconductor device according to claim 1 , wherein removing a portion from a surface of the semiconductor substrate to form a concave surface region comprises forming a thick oxide film by using a LOCOS method and removing the thick oxide film.

3. A method of manufacturing a semiconductor device according to claim 1 , wherein forming the source region of a second conductivity type and the drain region of the second conductivity type further comprises introducing an impurity under the same condition as a condition of an impurity introduction to a source region and a drain region of another transistor formed on the same semiconductor substrate.

4. A method of manufacturing a semiconductor device according to claim 1 , wherein forming the source region of a second conductivity type and the drain region of the second conductivity type further comprises introducing an impurity simultaneously with an impurity introduction to a source region and a drain region of another transistor formed on the same semiconductor substrate.

5. A method of manufacturing a semiconductor device according to claim 1 further comprising forming first electrical contacts to the source and drain regions in proximity to the trenches and second electrical contacts to the source and drain regions in the planar portion.

6. A method of manufacturing a semiconductor device comprising:

providing a substrate having an active surface region;

forming linear recesses in the active surface region;

forming a series of trenches in the active surface region intermediate to the linear recesses and spaced apart therefrom and leaving a planar portion of the active surface region between the trenches, the trenches having side surfaces,

wherein the linear recesses are separated from the side surfaces of the trenches by a constant distance, such that the linear recesses follow a contour of the side surfaces of the trench;

forming a gate insulating film on a side surface and a bottom surface of the trenches and on the planar portion of the active surface region;

forming a gate electrode on the gate insulating film that fills the trenches and extends on the planar portion of the active surface region and is separated from the linear recesses,

wherein the gate electrode extends farther in a channel length direction in the trenches than on the planar portion of active surface region; and

forming source and drain regions in the substrate below the linear recesses, such that the source and drain regions are adjacent to side surfaces of the trenches.

Assignments (4)
CHANGE OF NAME Recorded Mar 12, 2018
From: SII SEMICONDUCTOR CORPORATION
To: ABLIC INC.
Reel/Frame 045567/0927 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 037783 FRAME: 0166. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Feb 23, 2016
From: SEIKO INSTRUMENTS INC
To: SII SEMICONDUCTOR CORPORATION
Reel/Frame 037903/0928 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 11, 2016
From: SEIKO INSTRUMENTS INC
To: SII SEMICONDUCTOR CORPORATION .
Reel/Frame 037783/0166 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 23, 2008
From: HASHITANI, MASAYUKI
To: SEIKO INSTRUMENTS INC.
Reel/Frame 021572/0152 →