IP Library Granted Patent US 8,312,444
Granted Patent B2
US 8,312,444 · App. 12/179,715 · Granted Nov 13, 2012

Method for optimizing memory modules for user-specific environments

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,312,444
App. No.
12/179,715
Granted
Nov 13, 2012
Kind
B2
Abstract

A method for altering and preferably optimizing the performance of system memory of a computer system. The method includes identifying the motherboard and the memory module of the computer system, and then searching multiple SPD update files associated with multiple motherboards and containing data corresponding to physical and operational characteristics of multiple memory modules. From these SPD update files, a compatible SPD update file is identified that is compatible with the motherboard and contains data corresponding to physical and operational characteristics of the memory module. Thereafter, a software utility is used to erase pre-existing SPD data stored on the SPD circuit device and then write and verify installation of the data of the compatible SPD update file on the SPD circuit device. New SPD settings for the memory module are then enabled based on the data of the compatible SPD update file.

Claims (23)

1. A method for allowing an end-user to alter performance of a system memory of a computer system, the computer system comprising a motherboard and at least one memory module having a Serial Presence Detect (SPD) circuit device that contains data corresponding to physical and operational characteristics of the memory module, the method comprising:

Identifying the motherboard and identifying the at least one memory module by accessing and communicating with the SPD circuit device;

searching a plurality of SPD update files associated with a plurality of motherboards and containing data corresponding to physical and operational characteristics of a plurality of memory modules;

identifying module-specific SPD update files from the plurality of SPD update files based on the identified at least one memory module;

identifying a compatible SPD update file from the module-specific SPD update files based on the identified motherboard, the compatible SPD update file being associated with the motherboard and containing data corresponding to physical and operational characteristics of the at least one memory module;

the end-user using a software utility to erase pre-existing SPD data stored on the SPD circuit device and then write and verify the writing of the data of the compatible SPD update file on the SPD circuit device; and

enabling new SPD settings for the at least one memory module based on the data of the compatible SPD update file.

2. The method according to claim 1 , wherein the searching and identifying steps are performed over a network of computers.

3. The method according to claim 1 , wherein the searching and identifying steps are performed online over the Internet.

4. The method according to claim 3 , wherein the software utility and the compatible SPD update file are downloaded from the Internet.

5. The method according to claim 4 , wherein the software utility and the compatible SPD update file are provided on the Internet by a manufacturer of the at least one memory module.

6. The method according to claim 5 , wherein the searching step is performed by first identifying the motherboard among the plurality of motherboards, and then searching through the plurality of SPD update files which are associated with the motherboard.

7. The method according to claim 1 , wherein the searching step is performed by first identifying the motherboard among the plurality of motherboards, and then searching through the plurality of SPD update files which are associated with the motherboard.

8. The method according to claim 1 , wherein the new SPD settings enhance the performance of the at least one memory module for operation with the motherboard.

9. The method according to claim 1 , wherein the software utility accesses and communicates with the SPD circuit device through a system management bus of the motherboard.

10. The method according to claim 1 , wherein the SPD circuit device is an EEPROM Electrically Erasable Programmable Read Only Memory (EEPROM).

11. The method according to claim 1 , wherein the compatible SPD update file is a binary file.

12. The method according to claim 1 , further comprising backing-up the pre-existing data stored on the SPD circuit device prior to installing the data of the compatible SPD update file on the SPD circuit device.

13. The method according to claim 1 , wherein the enabling step comprises rebooting the computer system.

14. The method according to claim 1 , wherein the software utility verifies the installation of the compatible SPD update file by a process that comprises comparing at least one of the address space parameters, frequency, and latency settings of the at least one memory module and the compatible SPD update file.

15. The method according to claim 1 , wherein the method is performed following a firmware or BIOS upgrade on the motherboard.

16. The method according to claim 1 , wherein the method is performed to ensure proper operation of the at least one memory module on a different motherboard.

17. The method according to claim 1 , wherein the computer system operates with a Windows-based operating system.

Assignments (15)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 22, 2017
From: TOSHIBA CORPORATION
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043620/0430 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 14, 2016
From: OCZ STORAGE SOLUTIONS, INC.
To: TOSHIBA CORPORATION
Reel/Frame 038434/0371 →
RELEASE OF SECURITY INTEREST BY BANKRUPTCY COURT ORDER (RELEASES REEL/FRAME 030092/0739) Recorded Apr 8, 2014
From: HERCULES TECHNOLOGY GROWTH CAPITAL, INC.
To: OCZ TECHNOLOGY GROUP, INC.
Reel/Frame 032640/0284 →
RELEASE OF SECURITY INTEREST BY BANKRUPTCY COURT ORDER (RELEASES REEL/FRAME 031611/0168) Recorded Apr 8, 2014
From: COLLATERAL AGENTS, LLC
To: OCZ TECHNOLOGY GROUP, INC.
Reel/Frame 032640/0455 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE AND ATTACH A CORRECTED ASSIGNMENT DOCUMENT PREVIOUSLY RECORDED ON REEL 032365 FRAME 0920. ASSIGNOR(S) HEREBY CONFIRMS THE THE CORRECT EXECUTION DATE IS JANUARY 21, 2014. Recorded Mar 18, 2014
From: OCZ TECHNOLOGY GROUP, INC.
To: TAEC ACQUISITION CORP.
Reel/Frame 032461/0486 →
CHANGE OF NAME Recorded Feb 27, 2014
From: TAEC ACQUISITION CORP.
To: OCZ STORAGE SOLUTIONS, INC.
Reel/Frame 032365/0945 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2014
From: OCZ TECHNOLOGY GROUP, INC.
To: TAEC ACQUISITION CORP.
Reel/Frame 032365/0920 →
SECURITY AGREEMENT Recorded Nov 11, 2013
From: OCZ TECHNOLOGY GROUP, INC.
To: COLLATERAL AGENTS, LLC
Reel/Frame 031611/0168 →
SECURITY AGREEMENT Recorded Mar 27, 2013
From: OCZ TECHNOLOGY GROUP, INC.
To: HERCULES TECHNOLOGY GROWTH CAPITAL, INC.
Reel/Frame 030092/0739 →
RELEASE OF SECURITY INTEREST Recorded Mar 26, 2013
From: WELLS FARGO CAPITAL FINANCE, LLC, AS AGENT
To: OCZ TECHNOLOGY GROUP, INC.
Reel/Frame 030088/0443 →
SECURITY AGREEMENT Recorded May 14, 2012
From: OCZ TECHNOLOGY GROUP, INC.
To: WELLS FARGO CAPITAL FINANCE, LLC, AS AGENT
Reel/Frame 028440/0866 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 29, 2008
From: KHURJA, MICHAEL VON; LEACH, ANTHONY (NMN)
To: OCZ TECHNOLOGY GROUP, INC.
Reel/Frame 021598/0970 →