Low-power semi-dynamic flip-flop with smart keeper
View Patent ↗A modified high-speed flip-flop including an input circuit, a smart window circuit, a smart keeper circuit, a pre-charge circuit, a discharge circuit, a slave storage circuit, and an output circuit. Additionally, a circuit including the modified high-speed flip-flop, the circuit also including a non-zero operating voltage provided to the flip-flop, a common voltage provided to the flip-flop, a clock signal input to the flip-flop, a data signal input to the flip-flop wherein the data signal has a high state and a low state, and an output signal from the flip-flop wherein the output signal has a high state and a low state.
1. A modified high-speed flip-flop comprising:
an input circuit;
a smart window circuit;
a smart keeper circuit;
a pre-charge circuit;
a discharge circuit;
a slave storage circuit; and
an output circuit.
2. The flip-flop of claim 1 , wherein the smart keeper circuit provides a keeping force to maintain a non-zero node voltage at a node connecting the pre-charge circuit, discharge circuit, and output circuit.
3. The flip-flop of claim 2 , wherein the smart keeper circuit prevents contention between the pre-charge circuit and discharge circuit because the common node is always driven and never floated.
4. The flip-flop of claim 3 , wherein the power consumption of the flip-flop is reduced because a plurality of FETs used in the discharge circuit can be reduced in size and power consumption.
5. The flip-flop of claim 1 , wherein the flip-flop is disposed in a semiconductor device.
6. The flip-flop of claim 1 , wherein the flip-flop is disposed on a printed circuit board.
7. A circuit comprising:
a modified high-speed flip-flop comprising:
an input circuit,
a smart window circuit,
a smart keeper circuit,
a pre-charge circuit,
a discharge circuit,
a slave storage circuit, and
an output circuit;
a non-zero operating voltage provided to the flip-flop;
a common voltage provided to the flip-flop;
a clock signal input to the flip-flop;
a data signal input to the flip-flop wherein the data signal has a high state and a low state; and
an output signal from the flip-flop wherein the output signal has a high state and a low state;
wherein the high state refers to the operating voltage and the low state refers to the common voltage.
8. The circuit of claim 7 , wherein the smart keeper circuit provides a keeping force to maintain a non-zero node voltage at a node connecting the pre-charge circuit, discharge circuit, and output circuit.
9. The circuit of claim 8 , wherein the smart keeper circuit prevents contention between the pre-charge circuit and discharge circuit because the node is always driven and never floated.
10. The circuit of claim 9 , wherein the power consumption of the flip-flop is reduced because a plurality of FETs used in the discharge circuit can be reduced in size and power consumption.
11. The circuit of claim 7 , wherein the flip-flop is disposed in a semiconductor device.
12. The circuit of claim 7 , wherein the flip-flop is disposed on a printed circuit board.