Substrate with embedded patterned capacitance
View Patent ↗A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.
1. A process for forming a laminate with capacitance comprising:
providing a substrate;
laminating a valve metal conductive foil anode on said substrate wherein said foil comprises a metal oxide dielectric of said valve metal;
coating a solution or suspension of conductive layers on at least one discrete region of said dielectric to form at least one discrete cathode region;
treating said conductive foil to electrically isolate at least one region of said conductive foil containing said cathode region from remaining portion of said conductive foil.
2. The process for forming a laminate of claim 1 wherein said coating a solution or suspension of conductive layers takes place before said laminating said conductive foil to said substrate.
3. The process for forming a laminate of claim 1 , further comprising the step of removing at least one region of said conductive foil not comprising said cathode region.
4. The process for forming a laminate of claim 3 , comprising the step of removing at least one region of said conductive foil not comprising said cathode region prior to laminating said conductive foil to said substrate.
5. The process for forming a laminate of claim 1 further comprising laminating a second substrate over said conductive layers.
6. A laminate formed by the process of claim 5 .
7. The process for forming a laminate of claim 5 further comprising forming at least one plated through hole.
8. The process for forming a laminate of claim 1 further comprising the step of forming an electrical connection between at least one region of said conductive foil and a conductive trace.
9. The process for forming a laminate of claim 8 , wherein said electrical connection to said conductive trace comprises a via.
10. The process for forming a laminate of claim 1 further comprising the step of forming an electrical connection between said at least one cathode region and a conductive trace.
11. The process for forming a laminate of claim 10 , wherein said electrical connection to said conductive trace comprises a via.
12. The process for forming a laminate of claim 1 wherein said conductive foil comprises one conductor selected from aluminum, tantalum, niobium, titanium and NbO.
13. The process for forming a laminate of claim 12 wherein said conductive foil comprises aluminum.
14. The process for forming a laminate of claim 1 wherein said dielectric is an oxide of said conductive foil.
15. The process for forming a laminate of claim 1 wherein said treating said conductive foil is selected from routing, saw dicing, blade dicing, chemical etching, water jet cutting and laser cutting.
16. The process for forming a laminate of claim 1 wherein said substrate comprises a glass-reinforced polymer.
17. A capacitor formed by the method of claim 1 .
18. A process for forming a laminate with capacitance comprising:
providing a substrate;
laminating a valve metal conductive foil anode on said substrate wherein said foil comprises a metal oxide dielectric of said valve metal;
coating a solution or suspension of conductive layers on at least one discrete region of said dielectric to form at least one discrete cathode region;
treating said conductive foil to electrically isolate at least one region of said conductive foil containing said cathode region from remaining portion of said conductive foil;
further comprising forming at least one plated through hole;
further comprising laminating a second substrate over said conductive layers wherein said plated through hole is formed by steps of:
forming a first hole through said laminate in a region outside said cathode region;
filling said first hole with a non-conductive material;
forming a second hole through said non-conductive material, wherein said second hole has a smaller diameter than said first hole; and
applying a conductive material to said second hole to form a conductive pathway between a first face of said laminate and a second face of said laminate.
19. A process for forming a laminate with capacitance comprising:
providing a substrate;
laminating a conductive foil anode on said substrate wherein said foil comprises a dielectric of said conductive foil;
coating a solution or suspension of conductive layers on at least one discrete region of said dielectric to form at least one discrete cathode region;
treating said conductive foil to electrically isolate at least one region of said conductive foil containing said cathode region from remaining portion of said conductive foil;
wherein said conductive layers comprises a conductive polymeric material or manganese dioxide.
20. The process for forming a laminate of claim 19 wherein said conductive polymeric material comprises a material selected from polypyrrole, polyaniline, and polythiophene.
21. A process for forming a laminate with capacitance comprising:
providing a substrate;
laminating a valve metal conductive foil anode on said substrate wherein said foil comprises a metal oxide dielectric of said valve metal;
coating a solution or suspension of conductive polymeric directly on at least one discrete region of said dielectric to form at least one discrete cathode region;
treating said conductive foil to electrically isolate at least one region of said conductive foil containing said cathode region from remaining portion of said conductive foil.