VIDEO PROCESSING METHOD, VIDEO DISPLAY DEVICE AND ITS TIMING CONTROLLER
Video processing method, a video display device and its timing controller can support video signals having different types of resolutions from ones set in advance without a special circuit identifying the resolution. Timing controller of video display device generates a first horizontal reference signal (HRST_start) indicating start of an active period of a data enable signal and a second horizontal reference signal (HRST_end) indicating end of the active period from an input video signal. Next, timing controller generates control signals (HSP, STB, POL, VCK, and VOE) based on the number of clocks from the rise of the first and second horizontal reference signals (HRST_start and HRST_end) and on signal generation timing values (α, A to D) predetermined for each control signal supplied to drivers.
1 . A video processing method comprising:
having a timing controller of a video display device generate a first horizontal reference signal indicating the start of an active period of a data enable signal and a second horizontal reference signal indicating the end of said active period from an input video signal; and
having the timing controller of said video display device generate control signals based on the number of clocks from the rise of said first and second horizontal reference signals and on signal generation timing value determined for each of said control signals supplied to drivers.
2 . The video processing method as defined in claim 1 , wherein the timing controller of said video display device generates a horizontal start-pulse signal based on the number of clocks from the rise of said first horizontal reference signal and on signal generation timing value determined for said horizontal start-pulse signal.
3 . The video processing method as defined in claim 2 , wherein the timing controller of said video display device generates a vertical start-pulse signal that becomes active when a first horizontal start-pulse signal rises after a predetermined blanking period has lapsed and that remains so until a next horizontal start-pulse signal.
4 . The video processing method as defined in claim 1 wherein the timing controller of said video display device generates a data latch pulse STB, a polarity inversion signal POL, a gate driver shift clock VCK, and a gate driver output enable signal VOE based on the number of clocks from the rise of said second horizontal reference signal and on signal generation timing value determined for each of said control signals.
5 . The video processing method as defined in claim 2 , wherein a signal generation timing value for said horizontal start-pulse signal is a timing obtained by subtracting a predetermined number of clocks from a time obtained by adding an internal delay clock to the rise time of said first horizontal reference signal.
6 . The video processing method as defined in claim 4 , wherein a signal generation timing value for said data latch pulse STB is a timing obtained by subtracting a predetermined number of clocks from a time obtained by adding an internal delay clock to the rise time of said second horizontal reference signal.
7 . The video processing method as defined in claim 6 , wherein a signal generation timing value for said polarity inversion signal POL is a timing obtained by adding a predetermined number of clocks to the rise time of said data latch pulse STB.
8 . The video processing method as defined in claim 6 , wherein a signal generation timing value for said gate driver shift clock VCK and gate driver output enable signal VOE is a timing obtained by subtracting a predetermined number of clocks from the rise time of said data latch pulse STB.
9 . A timing controller of a video display device comprising:
a horizontal reference signal generating circuit that generates a first horizontal reference signal indicating the start of an active period of a data enable signal and a second horizontal reference signal indicating the end of said active period from an input video signal; and
a control signal generating circuit that generates control signals based on the number of clocks from the rise of said first and second horizontal reference signals and on signal generation timing value determined for each of said control signals supplied to drivers.
10 . The timing controller of a video display device as defined in claim 9 , wherein said control signal generating circuit generates a horizontal start-pulse signal based on the number of clocks from the rise of said first horizontal reference signal and on signal generation timing value determined for said horizontal start-pulse signal.
11 . The timing controller of a video display device as defined in claim 10 , wherein said control signal generating circuit generates a vertical start-pulse signal that becomes active when a first horizontal start-pulse signal rises after a predetermined blanking period has lapsed and that remains so until a next horizontal start-pulse signal.
12 . The timing controller of a video display device as defined in claim 9 , wherein said control signal generating circuit generates a data latch pulse STB, a polarity inversion signal POL, a gate driver shift clock VCK, and a gate driver output enable signal VOE based on the number of clocks from the rise of said second horizontal reference signal and on signal generation timing value determined for each of said control signals.
13 . The timing controller of a video display device as defined in claim 12 , wherein a signal generation timing value for said horizontal start-pulse signal is a timing obtained by subtracting a predetermined number of clocks from a time obtained by adding an internal delay clock to the rise time of said first horizontal reference signal.
14 . The timing controller of a video display device as defined in claim 13 , wherein a signal generation timing value for said data latch pulse STB is a timing obtained by subtracting a predetermined number of clocks from a time obtained by adding an internal delay clock to the rise time of said second horizontal reference signal.
15 . The timing controller of a video display device as defined in claim 14 , wherein a signal generation timing value for said polarity inversion signal POL is a timing obtained by adding a predetermined number of clocks to the rise time of said data latch pulse STB.
16 . The timing controller of a video display device as defined in claim 14 , wherein a signal generation timing value for said gate driver shift clock VCK and gate driver output enable signal VOE is a timing obtained by subtracting a predetermined number of clocks from the rise time of said data latch pulse STB.
17 . A video display device comprising the timing controller as defined in claim 9 .