Thin film transistor and flat panel display device including the same
View Patent ↗A thin film transistor includes a channel layer including an amorphous 12CaO.7Al 2 O 3 (C12A7) and a flat panel display device including the same. According to the present invention, the amorphous channel layer can be formed at a low temperature using C12A7. The thin film transistor including the amorphous channel layer has excellent electron mobility.
1. A thin film transistor, comprising:
a gate electrode formed on a substrate;
source and drain electrodes insulated from the gate electrode;
a channel layer insulated from the gate electrode and electrically connected to the source and drain electrodes; and
an insulating layer disposed between the channel layer and the gate electrode,
wherein the channel layer comprises an amorphous 12CaO.7Al 2 O 3 .
2. The thin film transistor of claim 1 , wherein the thickness of the channel layer is 5 to 200 nm.
3. The thin film transistor of claim 1 , wherein the channel layer is formed by heat-treating a film of 12CaO.7Al 2 O 3 deposited on the insulating layer at a temperature of 100 to 600° C.
4. The thin film transistor of claim 1 , wherein the substrate comprises one of a SUS substrate, a glass substrate, and a plastic substrate.
5. The thin film transistor of claim 1 , wherein a band gap value of the channel layer is 3 to 3.5 eV.
6. The thin film transistor of claim 1 , further comprising a buffer layer disposed on the substrate between the gate electrode and the substrate.
7. A thin film transistor, comprising:
source and drain electrodes formed on a substrate;
a gate electrode insulated from the source and drain electrodes;
a channel layer electrically connected to the source and drain electrodes, and insulated from the gate electrode; and
an insulating layer disposed between the channel layer and the gate electrode,
wherein the channel layer comprises an amorphous 12CaO.7Al 2 O 3 .
8. The thin film transistor of claim 7 , wherein the thickness of the channel layer is 5 to 200 nm.
9. The thin film transistor of claim 7 , wherein the channel layer is formed by heat treating a 12CaO.7Al 2 O 3 film deposited on the insulating layer at a temperature of 100 to 600° C.
10. The thin film transistor of claim 7 , wherein the substrate comprises one of a SUS substrate, a glass substrate, and a plastic substrate.
11. The thin film transistor of claim 7 , wherein a band gap value of the channel layer is 3 to 3.5 eV.
12. The thin film transistor of claim 7 , further comprising a buffer layer disposed on the substrate between the substrate and the source and drain electrodes and the channel layer.
13. A flat panel display device comprising:
the thin film transistor according to claim 1 ; and
a display device.
14. The flat panel display device of claim 13 , wherein the display device is one of an organic light-emitting device and a liquid crystal display device.
15. A flat panel display device comprising:
the thin film transistor according to claim 7 ; and
a display device.
16. The flat panel display device of claim 15 , wherein the display device is one of an organic light-emitting device and a liquid crystal display device.
17. A thin film transistor, comprising:
a gate electrode formed on a substrate;
an insulating layer disposed to cover the gate electrode;
a channel layer disposed on the insulating layer to correspond to the gate electrode; and
source and drain electrodes electrically connected to the channel layer,
wherein the channel layer comprises an amorphous 12CaO.7Al 2 O 3 .
18. The thin film transistor of claim 17 , further comprising a buffer layer disposed on the substrate between the gate electrode and the substrate.
19. The thin film transistor of claim 17 , wherein portions of each of the source and drain electrodes are disposed on the channel layer and the insulating layer.
20. A thin film transistor, comprising:
source and drain electrodes disposed on a substrate;
a channel layer disposed on the substrate to electrically connect the source and drain electrodes;
an insulating layer disposed to cover the source and drain electrodes and the channel layer; and
a gate electrode disposed on the insulating layer to correspond to the channel layer,
wherein the channel layer comprises an amorphous 12CaO.7Al 2 O 3 .
21. The thin film transistor of claim 20 , further comprising a buffer layer disposed on the substrate between the substrate and the source and drain electrodes and the channel layer.