Method for fabricating semiconductor device using two crystallization methods
View Patent ↗A semiconductor device in which a semiconductor layer of a thin film transistor and a first electrode of a capacitor are formed of amorphous silicon and the whole or a part of source/drain regions of the semiconductor layer and the first electrode of the capacitor are crystallized by a metal induced crystallization method, and a channel region of the semiconductor layer is crystallized by a metal induced lateral crystallization method.
1. A method for fabricating semiconductor device, comprising:
forming a semiconductor layer and a first electrode of a capacitor by depositing amorphous silicon on a substrate and patterning the amorphous silicon;
forming a first insulation layer on the semiconductor layer and the first electrode of the capacitor;
forming source/drain regions and a channel region of the semiconductor layer by implanting impurities into the semiconductor layer and implanting impurities into the first electrode of the capacitor;
forming a first insulation layer pattern on the channel region by etching the first insulation layer;
forming a crystallization inducing material on the semiconductor layer and the first electrode of the capacitor that are exposed by the first insulation layer pattern;
forming a second insulation layer on the crystallization inducing material; and
crystallizing regions of the source/drain regions and the first electrode of the capacitor by a metal induced crystallization method and crystallizing the channel region by a metal induced lateral crystallization method by heat treating the substrate.
2. The method of claim 1 , wherein the crystallization inducing material is formed by depositing at least one metal selected from Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo, Tr, Ru, Rh, Cd and Pt, heat treating the deposited metal, and removing any remaining metal.
3. The method of claim 1 , wherein the crystallization inducing material is formed to thickness of 10 to 200 Å.
4. The method of claim 1 , wherein the heat treating process is performed at a temperature of 400° C. to 700° C. for 1 to 18 hours.
5. The method of claim 1 , wherein the heat treating process is performed at a temperature of 500° C. to 600° C. for 3 to 12 hours.
6. The method of claim 1 , wherein forming the first insulation layer pattern exposes the first electrode of the capacitor and exposes either an entire region of the source/drain regions, an edge of the source/drain regions, a central part of the source/drain regions, or at least one region of the source/drain regions that is adjacent to an interface between the source/drain regions and the channel region.
7. The method of claim 1 , wherein forming the second insulation layer comprises forming a gate insulator of the thin film transistor and an insulation layer of the capacitor.
8. The method of claim 1 , wherein the first insulation layer pattern completely exposes the first electrode of the capacitor.
9. The method of claim 1 , wherein the crystallization inducing material is formed directly on an entire upper surface of the first electrode of the capacitor.